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    Searched refs:FirstOp (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ConditionalCompares.cpp 652 unsigned FirstOp = 1; // First CmpMI operand to copy.
665 case AArch64::FCMPSrr: Opc = AArch64::FCCMPSrr; FirstOp = 0; break;
666 case AArch64::FCMPDrr: Opc = AArch64::FCCMPDrr; FirstOp = 0; break;
667 case AArch64::FCMPESrr: Opc = AArch64::FCCMPESrr; FirstOp = 0; break;
668 case AArch64::FCMPEDrr: Opc = AArch64::FCCMPEDrr; FirstOp = 0; break;
672 FirstOp = 0;
678 FirstOp = 0;
690 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
692 if (CmpMI->getOperand(FirstOp + 1).isReg())
693 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg()
    [all...]
AArch64ISelLowering.cpp 9535 SDValue FirstOp = N->getOperand(0);
9536 unsigned FirstOpc = FirstOp.getOpcode();
9546 And = FirstOp;
9552 Shift = FirstOp;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizerInfo.h 1101 const unsigned OpcodeIdx = Aspect.Opcode - FirstOp;
1126 const unsigned OpcodeIdx = Opcode - FirstOp;
1137 const unsigned OpcodeIdx = Opcode - FirstOp;
1337 const unsigned OpcodeIdx = Opcode - FirstOp;
1344 const unsigned OpcodeIdx = Opcode - FirstOp;
1360 unsigned OpcodeIdx = Opcode - FirstOp;
1373 const unsigned OpcodeIdx = Opcode - FirstOp;
1473 static const int FirstOp = TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START;
1478 SmallVector<TypeMap, 1> SpecifiedActions[LastOp - FirstOp + 1];
1480 ScalarSizeChangeStrategies[LastOp - FirstOp + 1]
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerInfo.cpp 297 for (unsigned OpcodeIdx = 0; OpcodeIdx <= LastOp - FirstOp; ++OpcodeIdx) {
298 const unsigned Opcode = FirstOp + OpcodeIdx;
413 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode");
414 return Opcode - FirstOp;
460 assert(OpcodeTo >= FirstOp && OpcodeTo <= LastOp && "Unsupported opcode");
625 if (Aspect.Opcode < FirstOp || Aspect.Opcode > LastOp)
656 if (Aspect.Opcode < FirstOp || Aspect.Opcode > LastOp)
694 for (unsigned Opcode = FirstOp; Opcode <= LastOp; ++Opcode) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineInstr.cpp 1678 bool FirstOp = true;
1710 FirstOp = false;
1716 if (FirstOp) FirstOp = false; else OS << ",";
1784 if (!FirstOp) {
1785 FirstOp = false;
1792 if (!FirstOp) {
1793 FirstOp = false;
1800 if (!FirstOp) {
1801 FirstOp = false
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombinePHI.cpp 551 Value *FirstOp = FirstInst->getOperand(i);
552 PHINode *NewPN = PHINode::Create(FirstOp->getType(), e,
553 FirstOp->getName()+".pn");
556 NewPN->addIncoming(FirstOp, PN.getIncomingBlock(0));
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
NewGVN.cpp 1569 Value *FirstOp = lookupOperandLeader(CmpOp0);
1574 if (shouldSwapOperands(FirstOp, SecondOp)) {
1575 std::swap(FirstOp, SecondOp);
1581 return ExprResult::some(createVariableOrConstant(FirstOp),
1585 if (Predicate == CmpInst::FCMP_OEQ && isa<ConstantFP>(FirstOp) &&
1586 !cast<ConstantFP>(FirstOp)->isZero())
1587 return ExprResult::some(createConstantExpression(cast<Constant>(FirstOp)),
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 1583 unsigned FirstOp = CurOp++;
1590 getX86RegNum(MI.getOperand(FirstOp)), OS);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 2348 MachineInstr *FirstOp = nullptr;
2383 FirstOp = Op;
2405 DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,
2412 MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
ARMISelLowering.cpp 7404 SDValue FirstOp = Op.getOperand(0);
7405 if (!isa<ConstantSDNode>(FirstOp) &&
7407 [&FirstOp](SDUse &U) {
7408 return U.get().isUndef() || U.get() == FirstOp;
7410 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i32, FirstOp,
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 741 MachineOperand FirstOp = MI.getOperand(0);
749 .add(FirstOp)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 7054 unsigned FirstOp;
7077 FirstOp = 0;
7093 FirstOp = 1;
7101 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)))
7104 SDValue Base = N->getOperand(FirstOp + 1);
7165 int Offset = N->getConstantOperandVal(FirstOp);
7241 if (FirstOp == 1) // Store
PPCISelLowering.cpp 14357 SDValue FirstOp;
14361 FirstOp = Op.getOperand(i);
14362 if (!FirstOp.isUndef())
14368 if (Op.getOperand(i) != FirstOp && !Op.getOperand(i).isUndef())
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 2050 unsigned FirstOp = 1;
2073 FirstOp = 0;
2088 if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
2089 Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64)
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
InstructionSimplify.cpp 4560 auto FirstOp = static_cast<Instruction::CastOps>(CI->getOpcode());
4568 if (CastInst::isEliminableCastPair(FirstOp, SecondOp, SrcTy, MidTy, DstTy,

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