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    Searched refs:FirstReg (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
FunctionLoweringInfo.cpp 392 Register FirstReg;
400 if (!FirstReg) FirstReg = R;
403 return FirstReg;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AggressiveAntiDepBreaker.cpp 497 unsigned FirstReg = 0;
504 if (FirstReg != 0) {
506 State->UnionGroups(FirstReg, Reg);
509 FirstReg = Reg;
513 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64InstPrinter.cpp 1296 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1297 Reg = FirstReg;
1298 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1299 Reg = FirstReg;
1300 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1301 Reg = FirstReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 3365 unsigned FirstReg = Inst.getOperand(0).getReg();
3370 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc,
3382 unsigned FirstReg = Inst.getOperand(0).getReg();
3400 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
3423 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr),
3436 unsigned FirstReg = Inst.getOperand(0).getReg();
3443 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false,
3447 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false,
3451 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false,
3485 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 2258 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset,
2317 FirstReg = Op0->getOperand(0).getReg();
2319 if (FirstReg == SecondReg)
2421 Register FirstReg, SecondReg;
2429 FirstReg, SecondReg, BaseReg,
2436 MRI->constrainRegClass(FirstReg, TRC);
2442 .addReg(FirstReg, RegState::Define)
2456 .addReg(FirstReg)
2474 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg);
2475 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 4319 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4324 unsigned NumRegs = LastReg - FirstReg;
4333 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4356 unsigned ArgReg = ByValArgRegs[FirstReg + I];
4372 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4382 unsigned NumRegs = LastReg - FirstReg;
4396 unsigned ArgReg = ArgRegs[FirstReg + I];
4445 unsigned ArgReg = ArgRegs[FirstReg + I];
4519 unsigned FirstReg = 0;
4535 FirstReg = State->getFirstUnallocated(IntArgRegs)
    [all...]
MipsISelLowering.h 567 const Argument *FuncArg, unsigned FirstReg,
576 unsigned FirstReg, unsigned LastReg,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 1570 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs];
1571 Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() -
3501 unsigned FirstReg;
3502 auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch);
3512 int64_t PrevReg = FirstReg;
3582 FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(),
6157 unsigned FirstReg;
6158 OperandMatchResultTy Res = tryParseScalarRegister(FirstReg);
6167 bool isXReg = XRegClass.contains(FirstReg),
6168 isWReg = WRegClass.contains(FirstReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 1632 Register FirstReg = SwapOps ? FalseReg : TrueReg,
1638 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
1639 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
1641 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
1643 Register OldFirstReg = FirstReg;
1644 FirstReg = MRI.createVirtualRegister(FirstRC);
1645 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
1650 .addReg(FirstReg).addReg(SecondReg)
PPCISelLowering.cpp 6710 const unsigned FirstReg = State.AllocateReg(PPC::R9);
6712 assert(FirstReg && SecondReg &&
6715 CCValAssign::getCustomReg(ValNo, ValVT, FirstReg, RegVT, LocInfo));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FrameLowering.cpp 2265 unsigned FirstReg = 0;
2273 FirstReg = Count - 1;
2279 for (unsigned i = FirstReg; i < Count; i += RegInc) {
2299 bool IsFirst = i == FirstReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 4754 unsigned FirstReg = Reg;
4763 FirstReg = Reg = getDRegFromQReg(Reg);
4917 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4921 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E));
4925 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,

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