| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 379 // restore %g0, %g0, %i[0-7]
406 // restore %g0, %g0, %i[0-7]
417 && OrMI->getOperand(1).getReg() != SP::G0
418 && OrMI->getOperand(2).getReg() != SP::G0)
422 && OrMI->getOperand(1).getReg() != SP::G0
445 // restore %g0, %g0, %g0
[all...] |
| SparcFrameLowering.cpp | 224 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
225 .addReg(SP::G0);
|
| SparcInstrInfo.cpp | 322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
362 .addReg(SP::G0)
384 MIB.addReg(SP::G0);
|
| SparcISelDAGToDAG.cpp | 140 R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout()));
357 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
|
| SparcRegisterInfo.cpp | 73 Reserved.set(SP::G0);
|
| SparcAsmPrinter.cpp | 394 MI->getOperand(opNum+1).getReg() == SP::G0)
395 return; // don't print "+%g0"
|
| SparcISelLowering.cpp | 1027 .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)
3299 // r0-r7 -> g0-g7
3371 SDValue Hi = DAG.getCopyFromReg(Lo, dl, SP::G0, MVT::i32);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcInstPrinter.cpp | 68 case SP::G0: // jmp $addr | ret | retl
156 if (Op1.isReg() && Op1.getReg() != SP::G0) {
161 // Skip the second operand iff it adds nothing (literal 0 or %g0) and we've
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) ||
|
| /src/sys/arch/amiga/dev/ |
| itevar.h | 83 char G0;
|
| ite.c | 1414 case '(': /* G0 */
2095 ip->GL = ip->G0;
|
| /src/sys/arch/atari/dev/ |
| itevar.h | 75 char G0;
|
| ite.c | 739 sc->G0 = CSET_ASCII;
743 sc->GL = &sc->G0;
1266 sc->G0 = CSET_ASCII;
1270 sc->GL = &sc->G0;
1462 case '(': /* G0 */
1546 sc->sc_G0 = sc->G0;
1560 sc->G0 = sc->sc_G0;
1596 case '(': /* designated G0 */
1599 sc->G0 = CSET_ASCII;
1603 sc->G0 = CSET_DECGRAPH
[all...] |
| /src/sys/arch/x68k/dev/ |
| ite.c | 592 ip->G0 = CSET_ASCII;
596 ip->GL = &ip->G0;
1120 ip->G0 = CSET_ASCII;
1124 ip->GL = &ip->G0;
1335 case '(': /* G0 */
1421 ip->sc_G0 = ip->G0;
1436 ip->G0 = ip->sc_G0;
1476 case '(': /* designate G0 */
1479 ip->G0 = CSET_ASCII;
1483 ip->G0 = CSET_JISKANA
[all...] |
| itevar.h | 87 char G0, G1, G2, G3;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 136 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
461 if (Reg >= Sparc::G0 && Reg <= Sparc::G7)
462 regIdx = Reg - Sparc::G0;
537 Op->Mem.OffsetReg = Sparc::G0; // always 0
588 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
788 Operands.push_back(SparcOperand::MorphToMEMri(Sparc::G0, std::move(LHS)));
1208 // %g0 - %g7
|
| /src/external/gpl3/gdb/dist/gdb/stubs/ |
| sparc-stub.c | 110 enum regnames {G0, G1, G2, G3, G4, G5, G6, G7,
173 mov %g0, %wim ! Clear wim so that subsequent save
179 save %g0, %g0, %g0 ! Slip into next window
211 std %g0, [%sp + (24 + 0) * 4] ! registers[Gx]
254 save %g0, %g0, %g0 ! by causing a window_underflow trap
265 jmpl %l2, %g0 ! Restore old P
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/stubs/ |
| sparc-stub.c | 110 enum regnames {G0, G1, G2, G3, G4, G5, G6, G7,
173 mov %g0, %wim ! Clear wim so that subsequent save
179 save %g0, %g0, %g0 ! Slip into next window
211 std %g0, [%sp + (24 + 0) * 4] ! registers[Gx]
254 save %g0, %g0, %g0 ! by causing a window_underflow trap
265 jmpl %l2, %g0 ! Restore old P
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-sparc.c | 1445 as_warn (_("setx: illegal temporary register g0"));
3586 #define G0 0
3635 == (INSN_OR | RD (O7) | RS2 (G0))))
3645 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3648 or %o7, %g0, %rN
3650 or %rN, %g0, %o7
3653 or %rN, %g0, %o7 with nop. */
3656 || reg == G0 || reg == O7)
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-sparc.c | 1444 as_warn (_("setx: illegal temporary register g0"));
3585 #define G0 0
3634 == (INSN_OR | RD (O7) | RS2 (G0))))
3644 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3647 or %o7, %g0, %rN
3649 or %rN, %g0, %o7
3652 or %rN, %g0, %o7 with nop. */
3655 || reg == G0 || reg == O7)
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| DependenceAnalysis.cpp | 1412 APInt G0 = AM.abs();
1414 APInt Q = G0; // these need to be initialized
1415 APInt R = G0;
1416 APInt::sdivrem(G0, G1, Q, R);
1420 G0 = G1; G1 = R;
1421 APInt::sdivrem(G0, G1, Q, R);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 61 SP::G0, SP::G1, SP::G2, SP::G3,
|
| /src/external/gpl3/binutils/dist/bfd/ |
| elfxx-sparc.c | 3674 /* mov %g0, %o0 */
3991 #define G0 0
4045 == (INSN_OR | RD(O7) | RS2(G0)))
4053 != (INSN_OR | RS1(O7) | RS2(G0)))
4057 or %o7, %g0, %rN
4059 or %rN, %g0, %o7
4062 or %rN, %g0, %o7 with nop. */
4066 || reg == G0 || reg == O7)
|
| /src/external/gpl3/binutils.old/dist/bfd/ |
| elfxx-sparc.c | 3677 /* mov %g0, %o0 */
3994 #define G0 0
4048 == (INSN_OR | RD(O7) | RS2(G0)))
4056 != (INSN_OR | RS1(O7) | RS2(G0)))
4060 or %o7, %g0, %rN
4062 or %rN, %g0, %o7
4065 or %rN, %g0, %o7 with nop. */
4069 || reg == G0 || reg == O7)
|
| /src/external/gpl3/gdb.old/dist/bfd/ |
| elfxx-sparc.c | 3650 /* mov %g0, %o0 */
3965 #define G0 0
4019 == (INSN_OR | RD(O7) | RS2(G0)))
4027 != (INSN_OR | RS1(O7) | RS2(G0)))
4031 or %o7, %g0, %rN
4033 or %rN, %g0, %o7
4036 or %rN, %g0, %o7 with nop. */
4040 || reg == G0 || reg == O7)
|
| /src/external/gpl3/gdb/dist/bfd/ |
| elfxx-sparc.c | 3661 /* mov %g0, %o0 */
3976 #define G0 0
4030 == (INSN_OR | RD(O7) | RS2(G0)))
4038 != (INSN_OR | RS1(O7) | RS2(G0)))
4042 or %o7, %g0, %rN
4044 or %rN, %g0, %o7
4047 or %rN, %g0, %o7 with nop. */
4051 || reg == G0 || reg == O7)
|
