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Searched refs:GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK (Results 1 - 7 of 7) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_polaris_baco.c	`71 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 }, 163 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 },`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_sh_mask.h	`91 #define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80`
smu_7_1_1_sh_mask.h	`91 #define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80`
smu_7_0_1_sh_mask.h	`91 #define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80`
smu_7_1_0_sh_mask.h	`91 #define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80`
smu_7_1_2_sh_mask.h	`91 #define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80`
smu_7_1_3_sh_mask.h	`113 #define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80`

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