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Searched refs:GC_HWIP (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
soc15_common.h	81 uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \ 82 uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \ 83 uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \ 104 uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \ 105 uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \ 106 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \ 107 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \ 120 uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
amdgpu_navi10_reg_init.c	`39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));`
amdgpu_navi12_reg_init.c	`39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));`
amdgpu_navi14_reg_init.c	`39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));`
amdgpu_arct_reg_init.c	`39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));`
amdgpu_vega10_reg_init.c	`39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));`
amdgpu_psp_v11_0.c	`625 sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; 626 sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; 636 sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; 637 sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;`
amdgpu_vega20_reg_init.c	`39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));`
amdgpu_discovery.c	`119 [GC_HWIP] = GC_HWID,`
amdgpu_sdma_v5_0.c	`119 base = adev->reg_offset[GC_HWIP][0][1]; 123 base = adev->reg_offset[GC_HWIP][0][0];`
amdgpu.h	`685 GC_HWIP = 1,`

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