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    Searched refs:GEN8_MASTER_IRQ (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
interrupt.c 222 * GEN8_MASTER_IRQ is a special irq register,
460 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
474 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
491 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
handlers.c 2763 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_irq.c 1628 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1640 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1641 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1649 I915_WRITE(GEN8_MASTER_IRQ, 0);
1675 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2385 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2393 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2398 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2480 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2916 I915_WRITE(GEN8_MASTER_IRQ, 0)
    [all...]
i915_debugfs.c 456 I915_READ(GEN8_MASTER_IRQ));
532 I915_READ(GEN8_MASTER_IRQ));
i915_reg.h 7436 #define GEN8_MASTER_IRQ _MMIO(0x44200)

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