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    Searched refs:GENFC_WT_1__VSYNC_SEL_W__SHIFT (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_12_0_sh_mask.h 2272 #define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3
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  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_sh_mask.h 911 #define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3
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dcn_2_0_0_sh_mask.h 322 #define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3
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