| /src/sys/external/bsd/ena-com/ena_defs/ |
| ena_eth_io_defs.h | 307 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
309 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
320 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
326 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
336 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
337 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
339 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
342 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
346 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
361 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0
[all...] |
| ena_admin_defs.h | 1005 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1014 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1017 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1022 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1023 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1025 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1031 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1034 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1066 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1067 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0
[all...] |
| /src/sys/external/bsd/ena-com/ |
| ena_eth_io_defs.h | 308 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
310 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
321 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
327 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
337 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
338 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
340 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
343 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
347 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
362 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0
[all...] |
| ena_admin_defs.h | 933 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
942 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
945 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
950 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
951 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
953 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
959 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
962 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
994 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
995 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0
[all...] |
| ena_plat.h | 153 #define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))
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| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| cmd_parser.c | 385 FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
957 (cmd_val(s, i) & GENMASK(22, 2))
960 (cmd_val(s, i) & GENMASK(22, 18))
963 (cmd_val(s, i) & GENMASK(31, 2))
966 (cmd_val(s, i) & GENMASK(15, 0))
1138 gma = cmd_val(s, 2) & GENMASK(31, 3);
1237 v = (dword0 & GENMASK(21, 19)) >> 19;
1244 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1246 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1247 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1)
[all...] |
| mpt.h | 133 if (WARN(control & GENMASK(15, 1), "only support one MSI format\n"))
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| gvt.h | 474 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
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| cfg_space.c | 169 start &= ~GENMASK(3, 0);
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| handlers.c | 163 offset &= ~GENMASK(11, 0);
278 (((new) & GENMASK(31, 16)) \
279 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
312 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
707 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
722 sticky_mask = GENMASK(27, 26) | (1 << 24);
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/pinctrl/ |
| k210-fpioa.h | 15 #define K210_PCF_MASK GENMASK(7, 0)
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| /src/sys/external/bsd/common/include/linux/ |
| bitops.h | 118 #define GENMASK(h,l) ((unsigned long)__BITS(h,l))
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/ |
| nouveau_dispnv50_base907c.c | 109 return ret & GENMASK(18, 0);
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_ras_eeprom.c | 61 #define EEPROM_ADDR_MSB_MASK GENMASK(17, 8)
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_drv.h | 1404 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1420 GENMASK((e) - 1, (s) - 1))
1657 GENMASK(first__ + count__ - 1, first__)) >> first__; \
|
| intel_device_info.c | 541 subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
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| i915_cmd_parser.c | 498 #define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)
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| i915_reg.h | 140 * Local wrapper for GENMASK() to force u32, with compile time checks.
145 ((u32)(GENMASK(__high, __low) + \
7637 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
7638 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
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| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_client_modeset.c | 597 mask = GENMASK(count - 1, 0);
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| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_engine_cs.c | 443 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
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| intel_lrc.c | 179 #define GEN12_CSB_SW_CTX_ID_MASK GENMASK(25, 15)
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| selftest_lrc.c | 3694 if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
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| /src/sys/external/bsd/drm2/dist/drm/i915/gem/ |
| i915_gem_context.c | 2184 BUILD_BUG_ON(GENMASK(BITS_PER_TYPE(local.flags) - 1, ARRAY_SIZE(fn)) !=
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