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    Searched refs:GFX10 (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNSubtarget.h 422 return getGeneration() >= GFX10;
461 return getGeneration() >= AMDGPUSubtarget::GFX10;
819 bool hasPermLaneX16() const { return getGeneration() >= GFX10; }
826 return HasDPP && getGeneration() < GFX10;
830 return HasDPP && getGeneration() < GFX10;
846 return getGeneration() >= GFX10;
959 bool hasHardClauses() const { return getGeneration() >= GFX10; }
AMDGPUSubtarget.h 41 GFX10 = 9
GCNNSAReassign.cpp 10 /// \brief Try to reassign registers on GFX10+ from non-sequential to sequential
229 if (ST->getGeneration() < GCNSubtarget::GFX10)
AMDGPUSubtarget.cpp 336 if (getGeneration() < GFX10)
666 if (getGeneration() >= AMDGPUSubtarget::GFX10)
702 if (getGeneration() >= AMDGPUSubtarget::GFX10)
SIShrinkInstructions.cpp 711 ST.getGeneration() >= AMDGPUSubtarget::GFX10 &&
SIInstrInfo.cpp 350 // GFX10 possible NSA encoding.
4269 ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
4271 "wavefront shifts are not supported on GFX10+";
4275 ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
4277 "broadcasts are not supported on GFX10+";
4281 ST.getGeneration() < AMDGPUSubtarget::GFX10) {
4287 "GFX90A/GFX10";
4291 "row_share and row_xmask are not supported before GFX10";
4735 // we need to only have one constant bus use before GFX10.
4834 // but only one literal constant and only starting from GFX10
    [all...]
SIMemoryLegalizer.cpp 780 if (Generation < AMDGPUSubtarget::GFX10)
SIFrameLowering.cpp 273 if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
AMDGPUInstructionSelector.cpp 1252 if (STI.getGeneration() >= AMDGPUSubtarget::GFX10) {
1272 if (STI.getGeneration() >= AMDGPUSubtarget::GFX10)
SIISelLowering.cpp 6827 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10) {
6850 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10)
11909 // Pre-GFX10 target did not benefit from loop alignment
11911 (getSubtarget()->getGeneration() < AMDGPUSubtarget::GFX10) ||
11915 // On GFX10 I$ is 4 x 64 bytes cache lines.

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