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    Searched refs:GICC_EOIR (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arm/cortex/
gic_reg.h	53 #define GICC_EOIR 0x0010 // End Of Interrupt Register (WO) 302 #define GICv1_ICCEOIR GICC_EOIR
gic.c	396 gicc_write(sc, GICC_EOIR, iar);

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