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    Searched refs:GICD_ISENABLERn (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/arch/arm/cortex/
gic_reg.h 126 #define GICD_ISENABLERn(n) (0x100+4*(n)) // Interrupt Set-Enable Registers
289 #define GICv1_ICDISERn(n) GICD_ISENABLERn(n)
gic.c 206 gicd_write(sc, GICD_ISENABLERn(group), irq_mask);
554 gicd_write(sc, GICD_ISENABLERn(0),
653 gicd_write(sc, GICD_ISENABLERn(group), 0xffffffff);
654 uint32_t valid = gicd_read(sc, GICD_ISENABLERn(group));
gicv3.c 145 gicd_write_4(sc, GICD_ISENABLERn(group), mask);

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