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    Searched refs:GICR_ICENABLER0 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arm/cortex/
gic_reg.h	213 #define GICR_ICENABLER0 0x10180 // Interrupt Clear-Enable Register 0
gicv3.c	160 gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, mask); 296 gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, ~0);

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