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    Searched refs:GICR_ISENABLER0 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arm/cortex/
gic_reg.h	212 #define GICR_ISENABLER0 0x10100 // Interrupt Set-Enable Register 0
gicv3.c	141 gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, mask); 331 gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, sc->sc_enabled_sgippi);

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