HomeSort by: relevance | last modified time | path
    Searched refs:GPCPLL_CFG (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
gk20a.h 37 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0)
140 val = nvkm_rd32(device, GPCPLL_CFG);
nouveau_nvkm_subdev_clk_gk20a.c 266 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
267 nvkm_rd32(device, GPCPLL_CFG);
270 val = nvkm_rd32(device, GPCPLL_CFG);
273 nvkm_wr32(device, GPCPLL_CFG, val);
277 if (nvkm_wait_usec(device, 300, GPCPLL_CFG, GPCPLL_CFG_LOCK,
296 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
297 nvkm_rd32(device, GPCPLL_CFG);
566 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 1);
578 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 0);
579 nvkm_rd32(device, GPCPLL_CFG);
    [all...]
nouveau_nvkm_subdev_clk_gm20b.c 331 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
332 nvkm_rd32(device, GPCPLL_CFG);
338 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_SYNC_MODE,
340 nvkm_rd32(device, GPCPLL_CFG);
358 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_SYNC_MODE, 0);
360 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
361 nvkm_rd32(device, GPCPLL_CFG);
743 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 1);
825 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 0);
826 nvkm_rd32(device, GPCPLL_CFG);
    [all...]

Completed in 14 milliseconds