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    Searched refs:GPRArgRegs (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallingConv.cpp 68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
74 Reg = State.AllocateReg(GPRArgRegs);
ARMFastISel.cpp 3049 static const MCPhysReg GPRArgRegs[] = {
3056 unsigned SrcReg = GPRArgRegs[ArgNo];
ARMISelLowering.cpp 153 static const MCPhysReg GPRArgRegs[] = {
2688 unsigned Reg = State->AllocateReg(GPRArgRegs);
2695 Reg = State->AllocateReg(GPRArgRegs);
2708 while (State->AllocateReg(GPRArgRegs))
2725 State->AllocateReg(GPRArgRegs);
4161 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4162 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4300 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4301 if (RegIdx != array_lengthof(GPRArgRegs))
4302 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx])
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 5123 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
5126 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
5127 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
5143 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);

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