HomeSort by: relevance | last modified time | path
    Searched refs:GRPH_INT_CONTROL (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cik.c 6921 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
6922 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
6925 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
6926 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
6929 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6930 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
7273 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
7275 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
7279 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
7281 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET
    [all...]
cikd.h 939 #define GRPH_INT_CONTROL 0x685c
sid.h 866 #define GRPH_INT_CONTROL 0x685c
evergreend.h 1331 #define GRPH_INT_CONTROL 0x685c
radeon_evergreen.c 4484 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
4589 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
radeon_si.c 5974 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
6132 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h 870 #define GRPH_INT_CONTROL 0x1A17

Completed in 38 milliseconds