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    Searched refs:HALT (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 386 * Halt or unhalt the async dma engines (VI).
401 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
403 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
530 /* halt the engine before programing */
978 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
985 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
amdgpu_sdma_v3_0.c 560 * Halt or unhalt the async dma engines context switch (VI).
621 * Halt or unhalt the async dma engines (VI).
636 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
638 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
amdgpu_sdma_v5_0.c 535 * Halt or unhalt the async dma engines context switch (NAVI10).
589 * Halt or unhalt the async dma engines (NAVI10).
603 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
733 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
797 /* halt the MEs */
amdgpu_sdma_v4_0.c 992 * Halt or unhalt the async dma engines context switch (VEGA10).
1043 * Halt or unhalt the async dma engines (VEGA10).
1059 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1356 /* halt the MEs */
1431 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
  /src/sys/dev/qbus/
qduser.h 117 #define HALT 0x0000 /* halt DGA */
qd.c 709 dga->csr = (short) HALT; /* disable everything */
721 dga->csr = HALT; /* stop the wheels */
1017 dga->csr &= ~0x0600; /* halt the DMA! (just in case...) */
1742 dga->csr &= ~0x0600; /* halt DMA (reset fifo) */
2081 dga->csr &= ~0x0600; /* halt DMA (reset fifo) */
2132 dga->csr &= ~0x0600; /* halt DMA (reset fifo) */
3377 dga->csr &= ~(DMA_IE | 0x700); /* halt DMA and kill the intrpts */
  /src/sys/arch/vax/include/
qduser.h 124 #define HALT 0x0000 /* halt DGA */
  /src/sys/arch/luna68k/dev/xplx/
xplx.asm 827 HALT

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