| /src/sys/external/bsd/dwc2/dist/ |
| dwc2_hcdddma.c | 186 u32 hcfg; local in function:dwc2_per_sched_enable
191 hcfg = DWC2_READ_4(hsotg, HCFG);
192 if (hcfg & HCFG_PERSCHEDENA) {
200 hcfg &= ~HCFG_FRLISTEN_MASK;
201 hcfg |= fr_list_en | HCFG_PERSCHEDENA;
203 DWC2_WRITE_4(hsotg, HCFG, hcfg);
210 u32 hcfg; local in function:dwc2_per_sched_disable
215 hcfg = DWC2_READ_4(hsotg, HCFG)
[all...] |
| dwc2_hcdintr.c | 256 u32 hcfg; local in function:dwc2_hprt0_enable
290 hcfg = DWC2_READ_4(hsotg, HCFG);
291 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
299 "FS_PHY programming HCFG to 6 MHz\n");
302 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
303 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
304 DWC2_WRITE_4(hsotg, HCFG, hcfg);
310 "FS_PHY programming HCFG to 48 MHz\n")
396 u32 hcfg; local in function:dwc2_port_intr
[all...] |
| dwc2_core.c | 86 hr->hcfg = DWC2_READ_4(hsotg, HCFG);
121 DWC2_WRITE_4(hsotg, HCFG, hr->hcfg);
465 * Initializes the FSLSPClkSel field of the HCFG register depending on the
470 u32 hcfg, val; local in function:dwc2_init_fs_ls_pclk_sel
483 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
484 hcfg = DWC2_READ_4(hsotg, HCFG);
485 hcfg &= ~HCFG_FSLSPCLKSEL_MASK
1158 u32 hcfg, hfir, otgctl; local in function:dwc2_core_host_init
[all...] |
| dwc2_hw.h | 633 #define HCFG HSOTG_REG(0x0400)
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| dwc2_hcd.c | 1766 u32 hcfg; local in function:dwc2_hcd_hub_control
1770 hcfg = DWC2_READ_4(hsotg, HCFG);
1771 hcfg |= HCFG_DESCDMA;
1772 DWC2_WRITE_4(hsotg, HCFG, hcfg);
2309 dev_dbg(hsotg->dev, "hcfg=%08x\n", DWC2_READ_4(hsotg, HCFG));
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