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Searched refs:HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v8_0.c	`1466 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_sh_mask.h	`7376 #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0x0000000c`
dce_8_0_sh_mask.h	`5866 #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc`
dce_10_0_sh_mask.h	`6352 #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc [all...]`
dce_11_0_sh_mask.h	`6340 #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc [all...]`
dce_11_2_sh_mask.h	`7420 #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc [all...]`

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