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    Searched refs:HDMI_GENERIC_PACKET_CONTROL0 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_stream_encoder.c 85 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
92 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
99 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
106 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
113 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
120 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
127 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
134 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
173 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
183 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 72 SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
128 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
129 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
130 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
131 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
132 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
133 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
673 uint32_t HDMI_GENERIC_PACKET_CONTROL0;
amdgpu_dce_stream_encoder.c 216 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
222 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
816 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c 194 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
200 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
675 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
dcn10_stream_encoder.h 60 SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
142 uint32_t HDMI_GENERIC_PACKET_CONTROL0;

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