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    Searched refs:HDMI_NV_PDISP_SOR_PLL0_REG (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arm/nvidia/
tegra_hdmireg.h	198 #define HDMI_NV_PDISP_SOR_PLL0_REG 0x15c
tegra_drm_mode.c	933 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0); 973 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, 979 HDMI_SET_CLEAR(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG,

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