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    Searched refs:HDP (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_nv.c 46 #include "hdp/hdp_5_0_0_offset.h"
47 #include "hdp/hdp_5_0_0_sh_mask.h"
552 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
792 /* remap HDP registers to a hole in mmio space,
854 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
855 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
863 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
865 /* HDP 5.0 doesn't support dynamic power mode switch,
883 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
910 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl)
    [all...]
amdgpu_soc15.c 48 #include "hdp/hdp_4_0_offset.h"
49 #include "hdp/hdp_4_0_sh_mask.h"
830 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
833 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
1309 /* remap HDP registers to a hole in mmio space,
1383 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1397 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1399 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1407 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1536 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS))
    [all...]
amdgpu_gmc_v9_0.c 39 #include "hdp/hdp_4_0_offset.h"
40 #include "hdp/hdp_4_0_sh_mask.h"
1354 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
1360 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1362 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1363 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1365 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1366 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1368 /* After HDP is initialized, flush HDP.*
    [all...]
amdgpu_gmc_v10_0.c 34 #include "hdp/hdp_5_0_0_offset.h"
35 #include "hdp/hdp_5_0_0_sh_mask.h"
61 /* TODO add golden setting for hdp */
350 /* flush hdp cache */
932 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
934 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
936 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
937 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
939 /* Flush HDP after it is initialized */
amdgpu_gfx_v9_0.c 46 #include "hdp/hdp_4_0_offset.h"
1888 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4150 { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
6505 5 + /* hdp invalidate */
6540 5 + /* hdp invalidate */
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
stm32mp1-clks.h 70 #define HDP 55

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