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    Searched refs:HII (Results 1 - 23 of 23) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBranchRelaxation.cpp 68 const HexagonInstrInfo *HII;
95 HII = HST.getInstrInfo();
116 InstOffset += HII->getSize(MI);
118 if (MI.isBranch() && HII->isExtendable(MI))
150 if (HII->isExtended(MI))
159 InstOffset += HII->nonDbgBBSize(&B) * HEXAGON_INSTR_SIZE;
165 if (HII->analyzeBranch(B, TBB, FBB, Cond, false)) {
169 if (HII->isNewValueJump(*FirstTerm))
170 TBB = FirstTerm->getOperand(HII->getCExtOpNum(*FirstTerm)).getMBB();
175 return !HII->isJumpWithinBranchRange(*FirstTerm, Distance)
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HexagonVLIWPacketizer.cpp 115 const HexagonInstrInfo *HII = nullptr;
138 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
207 HII = HST.getInstrInfo();
214 HII->genAllInsnTimingClasses(MF);
247 HII->translateInstrsForDup(MF, true);
256 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
261 while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
276 HII->translateInstrsForDup(MF, false);
296 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
310 if (HII->isDeallocRet(MI)
    [all...]
HexagonHazardRecognizer.h 45 const HexagonInstrInfo *HII,
47 : Resources(ST.createDFAPacketizer(II)), TII(HII) { }
HexagonOptAddrMode.cpp 83 const HexagonInstrInfo *HII = nullptr;
129 if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI))
138 if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset)
140 return (HII->changeAddrMode_rr_ur(MI) >= 0);
141 else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset)
143 return (HII->changeAddrMode_io_abs(MI) >= 0);
196 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
326 switch (HII->getMemAccessSize(*MI)) {
345 return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false);
359 HII->getAddrMode(*MI) != HexagonII::BaseImmOffset |
    [all...]
HexagonFrameLowering.h 135 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
138 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
141 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
144 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
147 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
150 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
153 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
156 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
159 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
HexagonVExtract.cpp 55 const HexagonInstrInfo *HII = nullptr;
83 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L2_loadri_io), ElemR)
91 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::A2_andir), IdxR)
94 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L4_loadri_rr), ElemR)
103 HII = HST->getInstrInfo();
127 auto MIB = BuildMI(BB, At, dl, HII->get(FiOpc), AddrR);
156 BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc))
HexagonFrameLowering.cpp 591 auto &HII = *HST.getInstrInfo();
622 expandAlloca(MI, HII, SP, MaxCF);
638 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
704 BuildMI(MBB, InsertPt, dl, HII.get(LDOpc), RegUsed)
711 BuildMI(MBB, InsertPt, dl, HII.get(STOpc))
731 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io))
743 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
751 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
755 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
764 auto &HII = *HST.getInstrInfo()
    [all...]
HexagonFixupHwLoops.cpp 112 const HexagonInstrInfo *HII =
126 InstOffset += HII->getSize(MI);
139 unsigned InstSize = HII->getSize(*MII);
HexagonRDFOpt.cpp 220 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII());
221 if (HII.getAddrMode(MI) != HexagonII::PostInc)
273 MI.setDesc(HII.get(NewOpc));
294 const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
302 TargetOperandInfo TOI(HII);
303 DataFlowGraph G(MF, HII, HRI, *MDT, MDF, TOI);
HexagonEarlyIfConv.cpp 213 const HexagonInstrInfo *HII = nullptr;
482 if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3))
681 return MI->mayStore() && HII->isPredicable(const_cast<MachineInstr&>(*MI));
706 return HII->getCondOpcode(Opc, !IfTrue);
723 MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc));
725 if (HII->isPostIncrement(*MI)) {
742 const MCInstrDesc &D = HII->get(IfTrue ? Hexagon::J2_jumpt
799 const MCInstrDesc &D = HII->get(Opc);
909 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, HII->get(Hexagon::J2_jump)
    [all...]
HexagonExpandCondsets.cpp 165 const HexagonInstrInfo *HII = nullptr;
344 if (HII->isPredicated(*DefI))
422 if (HII->isPredicated(*DefI))
492 if (!HII->isPredicated(*DefI))
647 MIB = BuildMI(B, At, DL, HII->get(Opc))
652 MIB = BuildMI(B, At, DL, HII->get(Opc))
696 MI.setDesc(HII->get(TargetOpcode::COPY));
724 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
759 if (PredValid && HII->isPredicated(*MI))
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HexagonConstExtenders.cpp 381 const HexagonInstrInfo *HII = nullptr;
873 const MCInstrDesc &D = HII->get(ExtOpc);
1051 if (!isRegOffOpcode(Opc) || HII->isConstExtended(MI))
1062 // HII::getBaseAndOffsetPosition returns the increment position as "offset".
1063 if (HII->isPostIncrement(MI))
1066 const MCInstrDesc &D = HII->get(Opc);
1070 if (!HII->getBaseAndOffsetPosition(MI, BaseP, OffP) ||
1114 const MCInstrDesc &D = HII->get(IdxOpc);
1156 unsigned AM = HII->getAddrMode(MI);
1228 if (!HII->isConstExtended(MI)
    [all...]
HexagonSubtarget.cpp 251 const HexagonInstrInfo &HII, const SUnit &Inst1,
257 unsigned Type = HII.getType(*Inst2.getInstr());
271 auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
284 shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
336 const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
345 HII.getAddrMode(L0) != HexagonII::BaseImmOffset)
349 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
358 HII.getAddrMode(L1) != HexagonII::BaseImmOffset)
362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
HexagonBitSimplify.cpp 224 uint16_t Begin, const HexagonInstrInfo &HII);
624 BitVector &Bits, uint16_t Begin, const HexagonInstrInfo &HII) {
627 const MCInstrDesc &D = HII.get(Opc);
955 : MF(mf), HII(*MF.getSubtarget<HexagonSubtarget>().getInstrInfo()),
967 const HexagonInstrInfo &HII;
1053 RedundantInstrElimination(BitTracker &bt, const HexagonInstrInfo &hii,
1055 : Transformation(true), HII(hii), HRI(hri), MRI(mri), BT(bt) {}
1069 const HexagonInstrInfo &HII;
1254 bool GotBits = HBS::getUsedBits(Opc, OpN, T, Begin, HII);
    [all...]
HexagonISelDAGToDAG.h 31 const HexagonInstrInfo *HII;
36 : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
42 HII = HST->getInstrInfo();
HexagonGenMux.cpp 88 const HexagonInstrInfo *HII = nullptr;
162 const MCInstrDesc &D = HII->get(Opc);
252 bool IfTrue = HII->isPredicatedTrue(Opc);
343 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
386 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
HexagonRegisterInfo.cpp 215 auto &HII = *HST.getInstrInfo();
229 MI.setDesc(HII.get(Hexagon::A2_addi));
235 MI.setDesc(HII.get(Hexagon::A2_addi));
239 if (!HII.isValidOffset(Opc, RealOffset, this)) {
334 BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), ReuseBP)
HexagonVLIWPacketizer.h 73 const HexagonInstrInfo *HII;
HexagonSubtarget.h 82 bool shouldTFRICallBind(const HexagonInstrInfo &HII,
HexagonConstPropagation.cpp 1893 const HexagonInstrInfo &HII;
1926 HII(*Fn.getSubtarget<HexagonSubtarget>().getInstrInfo()),
2517 MI.setDesc(HII.get(Hexagon::A2_nop));
2890 &HII.get(Hexagon::PS_false) :
2891 &HII.get(Hexagon::PS_true);
2918 NewD = &HII.get(Hexagon::A2_tfrsi);
2923 NewD = &HII.get(Hexagon::A2_tfrpi);
2930 NewD = &HII.get(Hexagon::A2_combineii);
2936 NewD = &HII.get(Hexagon::CONST64);
3004 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR
    [all...]
HexagonGenInsert.cpp 568 const HexagonInstrInfo *HII = nullptr;
1078 bool DefEx = HII->isConstExtended(*DefVR);
1416 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert)
1417 : HII->get(Hexagon::S2_insertp);
1515 HII = ST.getInstrInfo();
1528 const HexagonEvaluator HE(*HRI, *MRI, *HII, MF);
HexagonAsmPrinter.cpp 761 const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
762 if (MI->isBundle() && HII.getBundleNoShuf(*MI))
HexagonISelDAGToDAG.cpp 78 bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc);
221 uint64_t F = HII->get(LoadN->getMachineOpcode()).TSFlags;
473 bool IsValidInc = HII->isValidAutoIncImm(StoredVT, Inc);
1287 BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)

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