| /src/sys/arch/zaurus/dev/ |
| ztp.c | 332 #define HSYNC() \
377 /* XXX poll hsync only if LCD is enabled */
382 HSYNC();
414 HSYNC();
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| am437x-sbc-t43.dts | 60 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
|
| imx53-mba53.dts | 146 /* VGA_VSYNC, HSYNC with max drive strength */
246 fsl,hsync-pin = <4>;
|
| imx6qdl-kontron-samx6i.dtsi | 588 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */
|
| am437x-sk-evm.dts | 372 AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
890 hsync-active = <0>;
|
| am43x-epos-evm.dts | 433 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
982 hsync-active = <0>;
|
| at91sam9g45.dtsi | 282 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
|
| am437x-gp-evm.dts | 293 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
1071 hsync-active = <0>;
1088 hsync-active = <0>;
|
| /src/sys/external/bsd/drm2/dist/drm/i2c/ |
| ch7006_mode.c | 127 .flags = DRM_MODE_FLAG_##hsynp##HSYNC | \
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_modes.c | 243 /* 3) Nominal HSync width (% of line period) - default 8 */
322 /* Fill in HSync values */
387 /* width of hsync as % of total line */
406 int hsync, hfront_porch, vodd_front_porch_lines; local in function:drm_gtf_mode_complex
511 hsync = H_SYNC_PERCENT * total_pixels / 100;
512 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
513 hsync = hsync * GTF_CELL_GRAN;
515 hfront_porch = hblank / 2 - hsync;
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| handlers.c | 2112 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
2122 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
2132 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
2142 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| icl_dsi.c | 861 /* BSPEC: hsync size should be atleast 16 pixels */
863 DRM_ERROR("hsync size < 16 pixels\n");
876 I915_WRITE(HSYNC(dsi_trans),
|
| intel_display.c | 5658 I915_READ(HSYNC(cpu_transcoder)));
7935 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8636 I915_WRITE(HSYNC(cpu_transcoder),
8708 tmp = I915_READ(HSYNC(cpu_transcoder));
8767 mode->hsync = drm_mode_hsync(mode);
14173 * The scanline counter increments at the leading edge of hsync.
14178 * start of vblank, which also occurs at start of hsync (on the
17724 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
18636 u32 hsync; member in struct:intel_display_error_state::intel_transcoder_error_state
18716 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder))
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_reg.h | 4307 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4692 /* VSYNC/HSYNC bits new with 965, default is to be set */
5269 /* Number of pixels in the hsync. */
5279 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5287 /* End of hblank, measured in pixels minus one from start of hsync */
5290 /* Start of hblank, measured in pixels minus one from start of hsync */
|
