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    Searched refs:HasBaseReg (Results 1 - 22 of 22) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86AsmPrinter.cpp 293 bool HasBaseReg = BaseReg.getReg() != 0;
294 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
296 HasBaseReg = false;
299 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
324 if (HasBaseReg)
360 bool HasBaseReg = BaseReg.getReg() != 0;
361 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
363 HasBaseReg = false;
374 if (HasBaseReg) {
392 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) {
    [all...]
X86ISelLowering.cpp     [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LoopStrengthReduce.cpp 347 bool HasBaseReg = false;
467 HasBaseReg = true;
473 HasBaseReg = true;
614 if (HasBaseReg && BaseRegs.empty()) {
616 OS << "**error: HasBaseReg**";
617 } else if (!HasBaseReg && !BaseRegs.empty()) {
619 OS << "**error: !HasBaseReg**";
1216 bool HasBaseReg, int64_t Scale,
1379 Offset, F.HasBaseReg, F.Scale, Fixup.UserInst))
1633 bool HasBaseReg, int64_t Scale
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
TargetTransformInfoImpl.h 200 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
274 int64_t BaseOffset, bool HasBaseReg,
278 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
865 bool HasBaseReg = (BaseGV == nullptr);
914 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
TargetTransformInfo.h 606 bool HasBaseReg, int64_t Scale,
687 int64_t BaseOffset, bool HasBaseReg,
1498 int64_t BaseOffset, bool HasBaseReg,
1524 bool HasBaseReg, int64_t Scale,
1850 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
1852 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
1910 int64_t BaseOffset, bool HasBaseReg,
1913 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
BasicTTIImpl.h 299 bool HasBaseReg, int64_t Scale,
304 AM.HasBaseReg = HasBaseReg;
334 int64_t BaseOffset, bool HasBaseReg,
339 AM.HasBaseReg = HasBaseReg;
TargetLowering.h 2326 /// If HasBaseReg is false, there is no base register.
2332 bool HasBaseReg = false;
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
TargetTransformInfo.cpp 339 bool HasBaseReg, int64_t Scale,
342 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
426 Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
429 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUPerfHintAnalysis.cpp 241 AM.HasBaseReg = !AM.BaseGV;
SILoadStoreOptimizer.cpp 1928 AM.HasBaseReg = true;
1953 AM.HasBaseReg = true;
SIISelLowering.cpp 1285 case 0: // r + i or just i, depending on HasBaseReg.
1290 if (AM.HasBaseReg) {
1345 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1348 if (AM.Scale == 1 && AM.HasBaseReg)
1364 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1367 if (AM.Scale == 1 && AM.HasBaseReg)
8840 AM.HasBaseReg = true;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CodeGenPrepare.cpp 3507 !NewAddrMode.HasBaseReg);
4648 if (AddrMode.HasBaseReg) {
4653 AddrMode.HasBaseReg = true;
4664 if (AddrMode.HasBaseReg)
4666 AddrMode.HasBaseReg = true;
4801 if (!AddrMode.HasBaseReg) {
4802 AddrMode.HasBaseReg = true;
4807 AddrMode.HasBaseReg = false;
TargetLoweringBase.cpp 1908 case 0: // "r+i" or just "i", depending on HasBaseReg.
1911 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1916 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 853 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
865 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 1891 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 4209 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
4216 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 17669 if (!AM.HasBaseReg && Scale == 2)
17695 return (Scale == 1) || (!AM.HasBaseReg && Scale == 2);
17742 if (Scale == 1 || (AM.HasBaseReg && Scale == -1))
17745 if (!AM.HasBaseReg && Scale == 2)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 4266 case 0: // "r+i" or just "i", depending on HasBaseReg.
4269 if (!AM.HasBaseReg) // allow "r+i".
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 1036 AM.HasBaseReg = true;
2075 AM.HasBaseReg = true;
2084 AM.HasBaseReg = true;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 15828 case 0: // "r+i" or just "i", depending on HasBaseReg.
15831 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
15836 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 11718 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
11723 return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 875 case 0: // "r+i" or just "i", depending on HasBaseReg.
878 if (!AM.HasBaseReg) // allow "r+i".

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