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    Searched refs:HasDef (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
StackMaps.h 83 bool HasDef;
87 return (HasDef ? 1 : 0) + Pos;
98 bool hasDef() const { return HasDef; }
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 171 bool HasDef = MCID.getNumDefs();
172 if (HasDef && !MI.getOperand(0).isReg())
184 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
187 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
206 if (HasDef && Reg0 == Reg1 &&
211 } else if (HasDef && Reg0 == Reg2 &&
227 if (HasDef) {
RegAllocFast.cpp 1109 bool HasDef = false;
1117 HasDef = true;
1129 HasDef = true;
1147 if (HasDef) {
StackMaps.cpp 63 : MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
468 assert(PatchPointOpers(&MI).hasDef() && "Stackmap has no return value.");
541 opers.isAnyReg() && opers.hasDef());
548 for (unsigned i = 0, e = (opers.hasDef() ? NArgs + 1 : NArgs); i != e; ++i)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 983 bool HasDef = false;
992 HasDef = true;
995 return HasDef || LiveCPSR;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 729 bool HasDef = false;
733 if (HasDef)
735 HasDef = true;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIWholeQuadMode.cpp 383 bool HasDef = false;
395 HasDef |= Overlap.any();
412 if (HasDef)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
StatepointLowering.cpp 336 bool HasDef = !SI.CLI.RetTy->isVoidTy();
337 if (HasDef) {
FastISel.cpp 774 bool HasDef = !I->getType()->isVoidTy();
802 if (IsAnyRegCC && HasDef) {
SelectionDAGBuilder.cpp 9120 bool HasDef = !CB.getType()->isVoidTy();
9154 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
9217 if (IsAnyRegCC && HasDef) {
9236 if (HasDef) {
9247 if (IsAnyRegCC && HasDef) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.cpp 5631 bool HasDef = MI.getDesc().getNumDefs();
5632 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5642 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5643 (HasDef && Reg0 == Reg2 && Tied2))

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