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    Searched refs:Hazard (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleHazardRecognizer.h 10 // hazard-avoidance heuristics for scheduling.
24 /// the hazard.
39 Hazard, // This instruction can't be emitted at this cycle.
53 /// getHazardType - Return the hazard type of emitting this node. There are
56 /// * Hazard: issuing this instruction would stall the machine. If some
65 /// instructions is about to be schedule. The hazard state should be
70 /// emitted, to advance the hazard state.
73 /// This overload will be used when the hazard recognizer is being used
86 /// This overload will be used when the hazard recognizer is being used
93 /// returns NoHazard. If, even though there is no hazard, it would be better t
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonHazardRecognizer.cpp 1 //===-- HexagonHazardRecognizer.cpp - Hexagon Post RA Hazard Recognizer ---===//
9 // This file defines the hazard recognizer for scheduling on Hexagon.
10 // Use a DFA based hazard recognizer.
28 LLVM_DEBUG(dbgs() << "Reset hazard recognizer\n");
45 LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);
46 HazardType RetVal = Hazard;
52 return Hazard;
54 // causes a hazard.
69 LLVM_DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", "
71 return Hazard;
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  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
9 // This file implements hazard recognizers for scheduling on PowerPC processors.
237 // PowerPC 970 Hazard Recognizer
271 // Structural hazard info.
320 /// getHazardType - We return hazard for any non-branch instruction that would
343 return Hazard;
349 return Hazard;
359 if (NumIssued == 4) return Hazard;
363 if (NumIssued >= 2) return Hazard;
398 // Update structural hazard information
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 1 //===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
75 return Hazard;
102 llvm_unreachable("reverse ARM hazard checking unsupported");
178 return (((O0 ^ O1) & DataMask) != 0) ? NoHazard : Hazard;
229 return Hazard;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ScoreboardHazardRecognizer.cpp 10 // encapsultes hazard-avoidance heuristics for scheduling, based on the
60 // completely bypasses the scoreboard hazard logic.
71 LLVM_DEBUG(dbgs() << "Disabled scoreboard hazard recognizer\n");
75 LLVM_DEBUG(dbgs() << "Using scoreboard hazard recognizer: Depth = "
159 LLVM_DEBUG(dbgs() << "*** Hazard in cycle +" << StageCycle << ", ");
161 return Hazard;
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZHazardRecognizer.cpp 1 //=-- SystemZHazardRecognizer.h - SystemZ Hazard Recognizer -----*- C++ -*-===//
9 // This file defines a hazard recognizer for the SystemZ scheduler.
78 return (fitsIntoCurrentGroup(SU) ? NoHazard : Hazard);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNHazardRecognizer.cpp 1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls ------------===//
9 // This file implements hazard recognizers for scheduling on GCN processors.
23 // Hazard Recoginizer Implementation
152 auto HazardType = IsHazardRecognizerMode ? NoopHazard : Hazard;
383 llvm_unreachable("hazard recognizer does not support bottom-up scheduling.");
394 // Can only be run in a hazard recognizer mode.
486 // No-op Hazard Detection
562 // to the clause, so we have a hazard.
571 // This SMRD hazard only affects SI.
723 // There is no hazard if the instruction does not use vector reg
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