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    Searched refs:HiHalf (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAGHVX.cpp 631 return OpRef(R.OpN & (Undef | Index | HiHalf));
648 HiHalf = 0x40000000,
649 Whole = LoHalf | HiHalf,
724 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf);
991 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 1709 MachineInstr *HiHalf =
1716 (void)HiHalf;
1717 LLVM_DEBUG(dbgs() << " "; HiHalf->dump(););
SIInstrInfo.cpp 6356 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
6371 Worklist.insert(&HiHalf);
6427 MachineInstr *HiHalf =
6446 legalizeOperands(*HiHalf, MDT);
6496 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
6510 Worklist.insert(&HiHalf);
SIISelLowering.cpp 3995 MachineInstr *HiHalf =
4009 TII->legalizeOperands(*HiHalf);
5414 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
5418 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf);
5430 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) :
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 4826 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4843 .addDef(HiHalf)
4851 .addUse(HiHalf);

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