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    Searched refs:HighBits (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64StackTagging.cpp 153 int HighBits = End - Offset < 8 ? (8 - (End - Offset)) * 8 : 0;
154 if (HighBits)
155 Cst = (Cst << HighBits) >> HighBits;
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineSimplifyDemanded.cpp 653 APInt HighBits(APInt::getHighBitsSet(
662 !DemandedMask.intersects(HighBits)) {
668 Known.One |= HighBits;
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGExpr.cpp 1970 unsigned HighBits = StorageSize - Offset - Info.Size;
1971 if (HighBits)
1972 Val = Builder.CreateShl(Val, HighBits, "bf.shl");
1973 if (Offset + HighBits)
1974 Val = Builder.CreateAShr(Val, Offset + HighBits, "bf.ashr");
2232 unsigned HighBits = StorageSize - Info.Size;
2233 if (HighBits) {
2234 ResultVal = Builder.CreateShl(ResultVal, HighBits, "bf.result.shl");
2235 ResultVal = Builder.CreateAShr(ResultVal, HighBits, "bf.result.ashr");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 3551 Register HighBits =
3555 HighBits)
3561 MIB.addReg(HighBits);
3710 Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3715 HighBits)
3722 MIB.addReg(HighBits);
AMDGPUISelDAGToDAG.cpp 1536 SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32);
1538 AMDGPU::V_MOV_B32_e32, DL, MVT::i32, HighBits);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 2037 APInt HighBits =
2039 HighBits.lshrInPlace(ShVal);
2040 HighBits = HighBits.trunc(BitWidth);
2042 if (!(HighBits & DemandedBits)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 10447 auto HighBits = APInt::getHighBitsSet(32, 32 - MemVT.getSizeInBits());
10448 if (DAG.MaskedValueIsZero(CmpOp, HighBits))

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