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    Searched refs:I5 (Results 1 - 18 of 18) sorted by relevancy

  /src/external/gpl3/gdb.old/dist/sim/common/
sim-endian.h 378 #define U8_1(I0,I1,I2,I3,I4,I5,I6,I7) \
380 | V8_1(I4,4) | V8_1(I5,5) | V8_1(I6,6) | V8_1(I7,7))
381 #define U16_1(I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15) \
383 | V16_1(I4,4) | V16_1(I5,5) | V16_1(I6,6) | V16_1(I7,7) \
389 #define U16_2(I0,I1,I2,I3,I4,I5,I6,I7) \
391 | V16_2(I4,4) | V16_2(I5,5) | V16_2(I6,6) | V16_2(I7,7) )
  /src/external/gpl3/gdb/dist/sim/common/
sim-endian.h 378 #define U8_1(I0,I1,I2,I3,I4,I5,I6,I7) \
380 | V8_1(I4,4) | V8_1(I5,5) | V8_1(I6,6) | V8_1(I7,7))
381 #define U16_1(I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15) \
383 | V16_1(I4,4) | V16_1(I5,5) | V16_1(I6,6) | V16_1(I7,7) \
389 #define U16_2(I0,I1,I2,I3,I4,I5,I6,I7) \
391 | V16_2(I4,4) | V16_2(I5,5) | V16_2(I6,6) | V16_2(I7,7) )
  /src/external/gpl3/gcc/dist/libgcc/soft-fp/
op-8.h 231 #define __FP_FRAC_SET_8(X, I7, I6, I5, I4, I3, I2, I1, I0) \
232 (X##_f[7] = I7, X##_f[6] = I6, X##_f[5] = I5, X##_f[4] = I4, \
  /src/external/gpl3/gcc.old/dist/libgcc/soft-fp/
op-8.h 234 #define __FP_FRAC_SET_8(X, I7, I6, I5, I4, I3, I2, I1, I0) \
235 (X##_f[7] = I7, X##_f[6] = I6, X##_f[5] = I5, X##_f[4] = I4, \
  /src/external/bsd/pcc/dist/pcc/arch/sparc64/
macdefs.h 149 #define I5 28
  /src/external/gpl3/gdb/dist/gdb/stubs/
sparc-stub.c 113 I0, I1, I2, I3, I4, I5, FP, I7,
  /src/external/gpl3/gdb.old/dist/gdb/stubs/
sparc-stub.c 113 I0, I1, I2, I3, I4, I5, FP, I7,
  /src/external/gpl3/binutils/dist/opcodes/
v850-opc.c 1116 #define I5 (D4U + 1)
1120 #define I5DIV1 (I5 + 1)
1290 #define IF2 {I5, R2}
1455 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
1624 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1636 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1679 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
  /src/external/gpl3/binutils.old/dist/opcodes/
v850-opc.c 1116 #define I5 (D4U + 1)
1120 #define I5DIV1 (I5 + 1)
1290 #define IF2 {I5, R2}
1455 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
1624 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1636 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1679 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
  /src/external/gpl3/gdb.old/dist/opcodes/
v850-opc.c 1116 #define I5 (D4U + 1)
1120 #define I5DIV1 (I5 + 1)
1290 #define IF2 {I5, R2}
1455 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
1624 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1636 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1679 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
  /src/external/gpl3/gdb/dist/opcodes/
v850-opc.c 1116 #define I5 (D4U + 1)
1120 #define I5DIV1 (I5 + 1)
1290 #define IF2 {I5, R2}
1455 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
1624 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1636 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1679 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/
SparcDisassembler.cpp 68 SP::I4, SP::I5, SP::I6, SP::I7 };
  /src/external/gpl3/binutils/dist/zlib/contrib/masmx64/
gvmat64.asm 7 ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
  /src/external/gpl3/binutils.old/dist/zlib/contrib/masmx64/
gvmat64.asm 7 ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
  /src/external/gpl3/gdb/dist/zlib/contrib/masmx64/
gvmat64.asm 7 ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
  /src/external/gpl3/gdb.old/dist/zlib/contrib/masmx64/
gvmat64.asm 7 ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 59 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
85 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
118 // Promote integers to %i0-%i5.
163 // Promote integers to %i0-%i5, using half the register.
535 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
652 // in registers %i0-%i5. Variable floating point arguments are never passed
653 // in floating point registers. They go on %i0-%i5 or on the stack like
1022 .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
1068 // This argument should go in %i0-%i5
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/
SparcAsmParser.cpp 143 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };

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