| /src/sys/arch/hppa/hppa/ |
| lock_stubs.S | 224 #define I64 \
231 I64 I64
232 I64 I64
233 I64 I64
234 I64 I64
235 I64 I6
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRuntimeLibcallSignatures.cpp | 524 Subtarget.hasAddr64() ? wasm::ValType::I64 : wasm::ValType::I32;
544 Params.push_back(wasm::ValType::I64);
564 Params.push_back(wasm::ValType::I64);
579 Rets.push_back(wasm::ValType::I64);
583 Rets.push_back(wasm::ValType::I64);
587 Rets.push_back(wasm::ValType::I64);
588 Params.push_back(wasm::ValType::I64);
602 Params.push_back(wasm::ValType::I64);
603 Params.push_back(wasm::ValType::I64);
617 Params.push_back(wasm::ValType::I64);
[all...] |
| WebAssemblyMCInstLower.cpp | 130 // All C++ exceptions are assumed to have a single i32 (for wasm32) or i64
134 Params.push_back(Subtarget.hasAddr64() ? wasm::ValType::I64
214 return wasm::ValType::I64;
|
| WebAssemblyAsmPrinter.cpp | 63 for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
115 case wasm::ValType::I64:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/ |
| WebAssemblyTypeUtilities.h | 30 I64 = unsigned(wasm::ValType::I64),
|
| WebAssemblyTypeUtilities.cpp | 24 if (Type == "i64")
25 return wasm::ValType::I64;
51 .Case("i64", WebAssembly::BlockType::I64)
64 .Case("i64", MVT::i64)
67 .Case("i64", MVT::i64)
84 return "i64";
131 case MVT::i64
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/alpha/ |
| vms.h | 137 enum avms_arg_type {I64, FF, FD, FG, FS, FT};
152 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \
153 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \
|
| alpha.cc | 9604 return I64;
|
| /src/sys/lib/libsa/ |
| loadfile_elf32.c | 85 #define I64(f) \
110 I64(ehdr->e_entry);
111 I64(ehdr->e_phoff);
112 I64(ehdr->e_shoff);
177 I64(phdr->p_offset);
178 I64(phdr->p_vaddr);
179 I64(phdr->p_paddr);
180 I64(phdr->p_filesz);
181 I64(phdr->p_memsz);
183 I64(phdr->p_align)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Demangle/ |
| RustDemangle.h | 37 I64,
|
| /src/external/gpl3/gcc.old/dist/gcc/config/ia64/ |
| ia64.h | 885 enum ivms_arg_type {I64, FF, FD, FG, FS, FT};
906 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \
907 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \
908 (CUM).atypes[6] = (CUM).atypes[7] = I64; \
923 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \
924 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \
925 (CUM).atypes[6] = (CUM).atypes[7] = I64; \
|
| ia64.cc | 5000 return I64;
|
| /src/external/apache2/llvm/dist/llvm/lib/Demangle/ |
| RustDemangle.cpp | 269 // | "x" // i64
330 Type = BasicType::I64;
360 case BasicType::I64:
361 print("i64");
536 case BasicType::I64:
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/BinaryFormat/ |
| Wasm.h | 394 I64 = WASM_TYPE_I64,
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| AMDGPUMetadata.h | 105 I64 = 9,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPULibFunc.h | 269 I64 = INT | B64,
|
| AMDGPULibFunc.cpp | 626 case 'l': res.ArgType = AMDGPULibFunc::I64; break;
732 case AMDGPULibFunc::I64: return "l";
881 case AMDGPULibFunc::I64: T = Type::getInt64Ty(C); break;
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| mips16-opc.c | 203 #define I64 INSN_ISA64
453 {"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 },
456 {"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 },
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| mips16-opc.c | 203 #define I64 INSN_ISA64
453 {"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 },
456 {"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 },
|
| /src/external/apache2/llvm/dist/llvm/lib/Support/ |
| AMDGPUMetadata.cpp | 85 YIO.enumCase(EN, "I64", ValueType::I64);
|
| /src/external/apache2/llvm/dist/llvm/lib/ObjectYAML/ |
| WasmYAML.cpp | 583 ECase(I64);
|
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| TargetInfo.cpp | 1864 // it as an i8/i16/i32/i64.
2849 // If Has64BitPointers, this is an {i64, i64}, so classify both
3427 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3494 // It is always safe to classify this as an integer type up to i64 that
4677 // LLVM will extend it and return i32 in r3, or i64 in r3:r4.
4738 // "Align" the register count when TY is i64.
5725 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5799 // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
7408 // i64 __gpr
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 8550 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
17102 /* .i64 is a pseudo-op, so the immediate must be a repeating
25115 shl should accept I8 I16 I32 I64,
25156 /* Add/sub take types I8 I16 I32 I64 F32. */
25193 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
25194 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
25195 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
25196 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
25199 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
25209 /* Right shift narrowing. Types accepted I16 I32 I64. *
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-arm.c | 8553 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
17105 /* .i64 is a pseudo-op, so the immediate must be a repeating
25118 shl should accept I8 I16 I32 I64,
25159 /* Add/sub take types I8 I16 I32 I64 F32. */
25196 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
25197 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
25198 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
25199 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
25202 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
25212 /* Right shift narrowing. Types accepted I16 I32 I64. *
[all...] |
