HomeSort by: relevance | last modified time | path
    Searched refs:I915_NUM_ENGINES (Results 1 - 25 of 26) sorted by relevancy

1 2

  /src/sys/external/bsd/drm2/dist/drm/i915/selftests/
igt_live_test.h 12 #include "gt/intel_engine.h" /* for I915_NUM_ENGINES */
22 unsigned int reset_engine[I915_NUM_ENGINES];
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
scheduler.h 44 struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
49 struct intel_vgpu *engine_owner[I915_NUM_ENGINES];
52 struct task_struct *thread[I915_NUM_ENGINES];
53 wait_queue_head_t waitq[I915_NUM_ENGINES];
gvt.h 152 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
153 struct list_head workload_q_head[I915_NUM_ENGINES];
154 struct intel_context *shadow[I915_NUM_ENGINES];
161 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
162 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
163 void *ring_scan_buffer[I915_NUM_ENGINES];
164 int ring_scan_buffer_size[I915_NUM_ENGINES];
197 u32 hws_pga[I915_NUM_ENGINES];
322 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
338 int ctx_mmio_count[I915_NUM_ENGINES];
    [all...]
debugfs.c 155 val &= (1 << I915_NUM_ENGINES) - 1;
169 for (id = 0; id < I915_NUM_ENGINES; id++) {
sched_policy.c 475 for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) {
vgpu.c 332 for (i = 0; i < I915_NUM_ENGINES; i++)
mmio_context.c 153 u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
scheduler.c 1268 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1283 bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
cmd_parser.c 586 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
3043 for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
handlers.c 1498 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
1695 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_gt_types.h 92 struct intel_engine_cs *engine[I915_NUM_ENGINES];
selftest_timeline.c 254 return i915_prandom_u32_max_state(I915_NUM_ENGINES, rnd);
521 timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
595 timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
intel_engine_types.h 123 I915_NUM_ENGINES
mock_engine.c 282 GEM_BUG_ON(id >= I915_NUM_ENGINES);
intel_gt.c 399 struct i915_request *requests[I915_NUM_ENGINES] = {};
intel_engine_cs.c 303 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
443 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
intel_reset.c 1378 BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
selftest_workarounds.c 38 } engine[I915_NUM_ENGINES];
selftest_hangcheck.c 794 struct active_engine threads[I915_NUM_ENGINES] = {};
selftest_lrc.c 2601 struct task_struct *tsk[I915_NUM_ENGINES] = {};
2602 struct preempt_smoke arg[I915_NUM_ENGINES];
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_gpu_error.h 196 atomic_t reset_engine_count[I915_NUM_ENGINES];
i915_drv.h 978 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1366 (id__) < I915_NUM_ENGINES; \
intel_device_info.c 935 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
intel_guc_submission.c 641 I915_NUM_ENGINES > GUC_WQ_SIZE);
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_context.c 280 e = kzalloc(struct_size(e, engines, I915_NUM_ENGINES), GFP_KERNEL);
291 GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES);

Completed in 80 milliseconds

1 2