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    Searched refs:IH_RB_WPTR (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_ih.c 60 WREG32(IH_RB_WPTR, 0);
91 WREG32(IH_RB_WPTR, 0);
amdgpu_navi10_ih.c 92 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
221 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
226 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
228 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
amdgpu_cz_ih.c 139 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
201 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
202 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
amdgpu_iceland_ih.c 139 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
201 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
202 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
amdgpu_tonga_ih.c 133 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
203 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
204 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
amdgpu_vega10_ih.c 182 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
387 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
402 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
405 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
sid.h 667 #define IH_RB_WPTR 0xF83
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_r600.c 3649 WREG32(IH_RB_WPTR, 0);
3761 WREG32(IH_RB_WPTR, 0);
4080 wptr = RREG32(IH_RB_WPTR);
4143 RREG32(IH_RB_WPTR);
cikd.h 813 #define IH_RB_WPTR 0x3e0c
sid.h 663 #define IH_RB_WPTR 0x3e0c
radeon_si.c 5950 WREG32(IH_RB_WPTR, 0);
6036 WREG32(IH_RB_WPTR, 0);
6224 wptr = RREG32(IH_RB_WPTR);
evergreend.h 1232 #define IH_RB_WPTR 0x3e0c
r600d.h 671 #define IH_RB_WPTR 0x3e0c
radeon_cik.c 6870 WREG32(IH_RB_WPTR, 0);
7014 WREG32(IH_RB_WPTR, 0);
7516 wptr = RREG32(IH_RB_WPTR);
radeon_evergreen.c 4688 wptr = RREG32(IH_RB_WPTR);

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