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    Searched refs:INLINEASM (Results 1 - 25 of 37) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp 90 case ISD::INLINEASM: break;
127 case ISD::INLINEASM: break;
453 case ISD::INLINEASM:
556 case ISD::INLINEASM:
InstrEmitter.cpp 1171 case ISD::INLINEASM:
1180 : TargetOpcode::INLINEASM;
1185 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1192 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1203 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1206 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1212 switch (InlineAsm::getKind(Flags)) {
1214 case InlineAsm::Kind_RegDef:
1225 case InlineAsm::Kind_RegDefEarlyClobber:
1226 case InlineAsm::Kind_Clobber
    [all...]
ScheduleDAGFast.cpp 24 #include "llvm/IR/InlineAsm.h"
482 if (Node->getOpcode() == ISD::INLINEASM ||
489 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
492 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
495 if (InlineAsm::isRegDefKind(Flags) ||
496 InlineAsm::isRegDefEarlyClobberKind(Flags) ||
497 InlineAsm::isClobberKind(Flags)) {
SelectionDAGDumper.cpp 176 case ISD::INLINEASM: return "inlineasm";
ScheduleDAGRRList.cpp 39 #include "llvm/IR/InlineAsm.h"
716 case ISD::INLINEASM:
1362 if (Node->getOpcode() == ISD::INLINEASM ||
1369 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1372 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1375 if (InlineAsm::isRegDefKind(Flags) ||
1376 InlineAsm::isRegDefEarlyClobberKind(Flags) ||
1377 InlineAsm::isClobberKind(Flags)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CompressJumpTables.cpp 79 if (MI.getOpcode() == AArch64::INLINEASM ||
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 955 /// INLINEASM - Represents an inline asm block. This node always has two
963 /// of operands that follow, etc. See InlineAsm.h.
970 INLINEASM,
MachineInstr.h 28 #include "llvm/IR/InlineAsm.h"
919 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
920 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
996 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
997 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1009 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1010 if (ExtraInfo & InlineAsm::Extra_MayStore)
1250 return getOpcode() == TargetOpcode::INLINEASM ||
1257 return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
1261 InlineAsm::AsmDialect getInlineAsmDialect() const
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonVectorPrint.cpp 26 #include "llvm/IR/InlineAsm.h"
102 unsigned ExtraInfo = InlineAsm::Extra_HasSideEffects;
103 BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM))
HexagonMachineScheduler.cpp 114 case TargetOpcode::INLINEASM:
170 case TargetOpcode::INLINEASM:
HexagonISelLowering.cpp 40 #include "llvm/IR/InlineAsm.h"
666 if ((Op.getOpcode() != ISD::INLINEASM &&
674 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
676 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
679 switch (InlineAsm::getKind(Flags)) {
682 case InlineAsm::Kind_RegUse:
683 case InlineAsm::Kind_Imm:
684 case InlineAsm::Kind_Mem:
687 case InlineAsm::Kind_Clobber:
688 case InlineAsm::Kind_RegDef
    [all...]
HexagonInstrInfo.cpp 2367 case TargetOpcode::INLINEASM:
2823 case Hexagon::INLINEASM:
4487 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSERegisterInfo.cpp 103 case Mips::INLINEASM: {
104 unsigned ConstraintID = InlineAsm::getMemoryConstraintID(MO.getImm());
106 case InlineAsm::Constraint_ZC: {
MipsInstrInfo.cpp 581 case TargetOpcode::INLINEASM:
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430InstrInfo.cpp 298 case TargetOpcode::INLINEASM:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 166 // So, here, we check for this case, and mutate the inlineasm to use
180 if (i < InlineAsm::Op_FirstOperand)
185 Kind = InlineAsm::getKind(Flag);
191 // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
194 if (Kind == InlineAsm::Kind_Imm) {
200 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
208 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
211 if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
212 && Kind != InlineAsm::Kind_RegDefEarlyClobber
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InlineAsmLowering.cpp 10 /// This file implements the lowering from LLVM IR inline asm to MIR INLINEASM
53 const InlineAsm *IA = cast<InlineAsm>(CB.getCalledOperand());
55 Flags |= InlineAsm::Extra_HasSideEffects;
57 Flags |= InlineAsm::Extra_IsAlignStack;
59 Flags |= InlineAsm::Extra_IsConvergent;
60 Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
70 if (OpInfo.Type == InlineAsm::isInput)
71 Flags |= InlineAsm::Extra_MayLoad;
72 else if (OpInfo.Type == InlineAsm::isOutput
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRInstrInfo.cpp 490 case TargetOpcode::INLINEASM:
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyAsmPrinter.cpp 551 assert(MI->getOpcode() == WebAssembly::INLINEASM);
  /src/external/apache2/llvm/dist/llvm/lib/Bitcode/Reader/
BitcodeAnalyzer.cpp 218 STRINGIFY_CODE(CST_CODE, INLINEASM)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2InstrInfo.cpp 532 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXSwapRemoval.cpp 425 case PPC::INLINEASM:
PPCRegisterInfo.cpp 1347 else if (OpC != TargetOpcode::INLINEASM &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVInstrInfo.cpp 766 case TargetOpcode::INLINEASM:
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FloatingPoint.cpp 42 #include "llvm/IR/InlineAsm.h"
1494 case TargetOpcode::INLINEASM:
1534 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI.getNumOperands();
1538 NumOps = InlineAsm::getNumOperandRegisters(Flags);
1550 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
1555 switch (InlineAsm::getKind(Flags)) {
1556 case InlineAsm::Kind_RegUse:
1559 case InlineAsm::Kind_RegDef:
1560 case InlineAsm::Kind_RegDefEarlyClobber:
1565 case InlineAsm::Kind_Clobber
    [all...]

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