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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
PHIEliminationUtils.cpp 29 // the copy before the call/invoke instruction. Similarly for an INLINEASM_BR
32 // instructions that are Calls with EHPad successors or INLINEASM_BR in a
48 // 2. Immediately BEFORE a call/inlineasm_br.
55 I->getOpcode() == TargetOpcode::INLINEASM_BR) {
TailDuplicator.cpp 631 // INLINEASM_BR instructions after 4b0aa5724fea, which demonstrates the same
635 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
TargetInstrInfo.cpp 1029 // INLINEASM_BR can jump to another block
1030 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
SplitKit.cpp 89 // If there is a landing pad or inlineasm_br successor, also find the
92 // are Calls with EHPad successors or INLINEASM_BR in a block. Further, we
99 MI.getOpcode() == TargetOpcode::INLINEASM_BR) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp 91 case ISD::INLINEASM_BR: break;
128 case ISD::INLINEASM_BR: break;
454 case ISD::INLINEASM_BR:
557 case ISD::INLINEASM_BR:
InstrEmitter.cpp 1172 case ISD::INLINEASM_BR: {
1178 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1179 ? TargetOpcode::INLINEASM_BR
ScheduleDAGFast.cpp 483 Node->getOpcode() == ISD::INLINEASM_BR) {
SelectionDAGDumper.cpp 177 case ISD::INLINEASM_BR: return "inlineasm_br";
ScheduleDAGRRList.cpp 717 case ISD::INLINEASM_BR:
1363 Node->getOpcode() == ISD::INLINEASM_BR) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CompressJumpTables.cpp 80 MI.getOpcode() == AArch64::INLINEASM_BR)
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 972 /// INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
973 INLINEASM_BR,
MachineInstr.h 1251 getOpcode() == TargetOpcode::INLINEASM_BR;
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430InstrInfo.cpp 299 case TargetOpcode::INLINEASM_BR: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 332 case ISD::INLINEASM_BR: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.cpp 115 case TargetOpcode::INLINEASM_BR:
171 case TargetOpcode::INLINEASM_BR:
HexagonISelLowering.cpp 667 Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
1504 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom);
3120 if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRInstrInfo.cpp 491 case TargetOpcode::INLINEASM_BR: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2InstrInfo.cpp 532 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
ARMBaseInstrInfo.cpp 798 case ARM::INLINEASM_BR: {
2051 // INLINEASM_BR can jump to another block
2052 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
2624 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsInstrInfo.cpp 582 case TargetOpcode::INLINEASM_BR: { // Inline Asm: Variable size.
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXSwapRemoval.cpp 426 case PPC::INLINEASM_BR:
PPCRegisterInfo.cpp 1348 OpC != TargetOpcode::INLINEASM_BR) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVInstrInfo.cpp 767 case TargetOpcode::INLINEASM_BR: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FloatingPoint.cpp 1495 case TargetOpcode::INLINEASM_BR: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 1565 case SystemZ::INLINEASM_BR:

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