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    Searched refs:INTEL (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/arch/x86/pci/
dwiic_pci.c 75 { .id = VIDDID(INTEL, CORE4G_M_S_I2C_0) },
76 { .id = VIDDID(INTEL, CORE4G_M_S_I2C_1) },
77 { .id = VIDDID(INTEL, 100SERIES_I2C_0) },
78 { .id = VIDDID(INTEL, 100SERIES_I2C_1) },
79 { .id = VIDDID(INTEL, 100SERIES_I2C_2) },
80 { .id = VIDDID(INTEL, 100SERIES_I2C_3) },
81 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_0) },
82 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_1) },
83 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_2) },
84 { .id = VIDDID(INTEL, 100SERIES_LP_I2C_3) }
    [all...]
  /src/sys/arch/x86/x86/
est.c 55 * This is a driver for Intel's Enhanced SpeedStep Technology (EST),
60 * - IA-32 Intel Architecture Software Developer's Manual, Volume 3:
62 * Section 13.14, Enhanced Intel SpeedStep technology.
64 * http://www.intel.com/design/pentium4/manuals/253668.htm
66 * - Intel Pentium M Processor Datasheet.
68 * http://www.intel.com/design/mobile/datashts/252612.htm
70 * - Intel Pentium M Processor on 90 nm Process with 2-MB L2 Cache Datasheet
72 * http://www.intel.com/design/mobile/datashts/302189.htm
121 /* Ultra Low Voltage Intel Pentium M processor 900 MHz */
128 /* Ultra Low Voltage Intel Pentium M processor 1.00 GHz *
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  /src/sys/external/bsd/drm2/dist/include/uapi/drm/
drm_fourcc.h 4 * Copyright 2011 Intel Corporation
349 /* Intel framebuffer modifiers */
352 * Intel X-tiling layout
363 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
366 * Intel Y-tiling layout
378 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
381 * Intel Yf-tiling layout
393 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
396 * Intel color control surface (CCS) for render compression
412 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4
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  /src/sys/dev/mii/
ihphy.c 58 * Driver for Intel's 82577 (Hanksville) Ethernet 10/100/1000 PHY
59 * Data Sheet: http://download.intel.com/design/network/datashts/319439.pdf
96 MII_PHY_DESC(INTEL, I82577),
97 MII_PHY_DESC(INTEL, I82579),
98 MII_PHY_DESC(INTEL, I217),
99 MII_PHY_DESC(INTEL, I82580),
100 MII_PHY_DESC(INTEL, I350),
152 /* Link setup (as done by Intel's Linux driver for the 82577). */
  /src/external/gpl3/gcc/dist/gcc/config/i386/
x86-tune-sched-atom.cc 134 if (!TARGET_CPU_P (SILVERMONT) && !TARGET_CPU_P (INTEL))
208 && !TARGET_CPU_P (INTEL))
i386.cc 2988 /* Intel MCU psABI passes scalars and aggregates no larger than 8
3226 /* Intel MCU psABI passes scalars and aggregates no larger than 8
4375 /* Intel MCU psABI returns scalars and aggregates no larger than 8
6172 /* AMD and Intel CPUs prefer each a different instruction as loop filler.
13772 /* Intel syntax. For absolute addresses, registers should not
13860 /* Opcodes don't get size suffixes if using Intel opcodes. */
13900 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14158 /* Output 'qword ptr' for intel assembler dialect. */
14992 destination register is not st(0). The Intel assembler
18083 /* Compute the alignment for a variable for Intel MCU psABI. TYPE i
    [all...]
  /src/external/gpl3/gcc.old/dist/gcc/config/i386/
x86-tune-sched-atom.cc 134 if (!TARGET_CPU_P (SILVERMONT) && !TARGET_CPU_P (INTEL))
208 && !TARGET_CPU_P (INTEL))
i386.cc 2897 /* Intel MCU psABI passes scalars and aggregates no larger than 8
3131 /* Intel MCU psABI passes scalars and aggregates no larger than 8
4260 /* Intel MCU psABI returns scalars and aggregates no larger than 8
5959 /* AMD and Intel CPUs prefer each a different instruction as loop filler.
13090 /* Intel syntax. For absolute addresses, registers should not
13178 /* Opcodes don't get size suffixes if using Intel opcodes. */
13212 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
13469 /* Output 'qword ptr' for intel assembler dialect. */
14314 destination register is not st(0). The Intel assembler
17301 /* Compute the alignment for a variable for Intel MCU psABI. TYPE i
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  /src/sys/dev/pci/
auich.c 94 * AC'97 audio found on Intel 810/820/440MX chipsets.
95 * http://developer.intel.com/design/chipsets/datashts/290655.htm
96 * http://developer.intel.com/design/chipsets/manuals/298028.htm
97 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm
98 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm
99 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm
110 * http://www.intel.com/design/chipsets/specupdt/245051.htm
369 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA)
370 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA)
371 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA
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  /src/external/bsd/ntp/dist/scripts/monitoring/
ntploopstat 204 eval 'sub INTEL {1;}' unless defined(&INTEL);

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