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    Searched refs:INTERLACE (Results 1 - 19 of 19) sorted by relevancy

  /src/sys/arch/arm/amlogic/
meson_genfb.c 69 #define INTERLACE __BIT(0)
76 { 5, 1920, 1080, INTERLACE },
77 { 6, 720, 480, DBLSCAN | INTERLACE },
78 { 7, 720, 480, DBLSCAN | INTERLACE },
85 { 20, 1920, 1080, INTERLACE },
90 { 39, 1920, 1080, INTERLACE },
338 prop_dictionary_get_bool(cfg, "interlace", &interlace_p);
416 prop_dictionary_get_bool(cfg, "interlace", &interlace_p);
475 /* interlace */
581 prop_dictionary_set_bool(cfg, "interlace", !!(flags & INTERLACE))
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/include/
bios_parser_types.h 181 uint32_t INTERLACE:1;
grph_object_ctrl_defs.h 121 uint32_t INTERLACE:1;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_optc.c 56 if (timing->flags.INTERLACE == 1) {
251 if (patched_crtc_timing.flags.INTERLACE == 1)
255 /* Interlace */
257 if (patched_crtc_timing.flags.INTERLACE == 1)
328 /* Interlace */
330 if (patched_crtc_timing.flags.INTERLACE == 1) {
541 if (timing->flags.INTERLACE == 1)
561 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
amdgpu_dcn10_stream_encoder.c 274 if (hw_crtc_timing.flags.INTERLACE) {
275 /*the input timing is in VESA spec format with Interlace flag =1*/
amdgpu_dcn10_hw_sequencer.c 3097 if (timing->flags.INTERLACE == 1) {
3118 interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_hw_types.h 649 uint32_t INTERLACE :1;
dc_types.h 274 uint32_t INTERLACE :1;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 74 if (timing->flags.INTERLACE == 1) {
342 if (patched_crtc_timing.flags.INTERLACE == 1)
343 bp_params.flags.INTERLACE = 1;
1142 if (timing->flags.INTERLACE == 1)
amdgpu_dce110_timing_generator_v.c 383 timing->flags.INTERLACE,
amdgpu_dce110_hw_sequencer.c 1144 stream->timing.flags.INTERLACE;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
amdgpu_command_table2.c 541 if (bp_params->flags.INTERLACE) {
amdgpu_command_table.c 1787 if (bp_params->flags.INTERLACE) {
1866 if (bp_params->flags.INTERLACE) {
amdgpu_bios_parser.c 1284 info->lcd_timing.misc_info.INTERLACE =
1285 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace;
1402 info->lcd_timing.misc_info.INTERLACE =
1403 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace;
amdgpu_bios_parser2.c 921 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 301 if (hw_crtc_timing.flags.INTERLACE) {
302 /*the input timing is in VESA spec format with Interlace flag =1*/
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 111 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 1197 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1203 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 1956 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;

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