/src/sys/arch/riscv/riscv/ |
spl.S | 57 INT_L t0, CI_CPL(a3) // get current IPL 63 INT_L a1, 0(a1) 73 INT_L t4, CI_SOFTINTS(a3) // get softint mask 120 INT_L t5, IPL_VM * (1 << INT_SCALESHIFT)(t3) 137 INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTCLOCK 144 INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTBIO 151 INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTNET 158 INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTSERIAL 165 INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_VM 172 INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SCHE [all...] |
/src/lib/libc/compat/arch/mips/sys/ |
compat_sigsuspend.S | 51 INT_L a0, 0(a0) # indirect to mask arg
|
compat_sigprocmask.S | 54 INT_L a1, 0(a1) # indirect to new mask arg
|
/src/sys/arch/mips/mips/ |
lock_stubs_llsc.S | 229 INT_L a0, MTX_IPL(t0) 231 INT_L ta1, CPU_INFO_CPL(t2) 253 INT_L ta2, CPU_INFO_MTX_COUNT(t2) 261 INT_L ta1, CPU_INFO_MTX_OLDSPL(t2) 262 INT_L ta2, CPU_INFO_CPL(t2) # get updated CPL 293 INT_L t0, MTX_LOCK(a0) 305 INT_L a2, MTX_IPL(a0) 307 INT_L a0, CPU_INFO_MTX_OLDSPL(t2) 312 INT_L t0, CPU_INFO_MTX_COUNT(t2) 319 INT_L a1, CPU_INFO_CPL(t2 [all...] |
lock_stubs_ras.S | 136 INT_L t0, (a0) /* <- critical section start */ 366 INT_L a0, MTX_IPL(t0) 368 INT_L ta1, CPU_INFO_CPL(t2) # get current cpl 385 INT_L ta2, CPU_INFO_MTX_COUNT(t2) 395 INT_L t3, MTX_LOCK(t0) 417 INT_L t0, MTX_LOCK(a0) 430 INT_L a2, MTX_IPL(a0) 432 INT_L a0, CPU_INFO_MTX_OLDSPL(t2) 437 INT_L t0, CPU_INFO_MTX_COUNT(t2) 445 INT_L a1, CPU_INFO_CPL(t2 [all...] |
spl.S | 73 INT_L v0, CPU_INFO_CPL(a3) # get current IPL from cpu_info 122 INT_L a2, CPU_INFO_CPL(a3) # get IPL from cpu_info 134 INT_L a1, (v1) # load SR bits for this IPL 160 INT_L a1, (v1) # load SR bits for this IPL 173 INT_L v1, _C_LABEL(ipl_sr_map) + 4*IPL_NONE 247 INT_L a0, (v1) 254 INT_L v0, CPU_INFO_CPL(a3) # get current IPL from cpu_info 288 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_DDB 295 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_SCHED 302 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_V [all...] |
cache_r5k_subr.S | 45 INT_L t2, _C_LABEL(mips_cache_info)+MCI_SDCACHE_SIZE
|
locore_mips1.S | 110 INT_L k0, 0(k1) #0f: k0=lo0 pte 280 INT_L t1, CPU_INFO_CPL(t0) # get current priority level 323 INT_L t2, TF_BASE+TF_PPL(sp) # get saved priority level 326 INT_L t1, CPU_INFO_CPL(t0) # get current priority level 410 INT_L k0, CPU_INFO_IDEPTH(k0) # grab interrupt depth 461 INT_L s0, CPU_INFO_CPL(s2) 496 INT_L t1, CPU_INFO_IDEPTH(s2) # we need to inc. intr depth 550 INT_L t0, CPU_INFO_SOFTINTS(s2) # get pending softints 570 INT_L t0, TF_BASE+TF_PPL(sp) # get saved priority level 690 INT_L v0, L_MD_ASTPENDING(MIPS_CURLWP)# any pending ast [all...] |
mipsX_subr.S | 467 INT_L k0, 0(k1) #0f: k0=lo0 pte 491 INT_L k0, 0(k1) #0f: k0=lo0 pte 492 INT_L k1, 4(k1) #10: k1=lo1 pte 789 INT_L t1, CPU_INFO_CPL(t0) # get current priority level 856 INT_L t2, TF_BASE+TF_PPL(sp) # get saved priority level 858 INT_L t1, CPU_INFO_CPL(t0) # get current priority level 1013 INT_L t1, CPU_INFO_CPL(t0) # get current priority level 1081 INT_L k0, CPU_INFO_IDEPTH(k0) # grab interrupt depth 1133 INT_L s0, CPU_INFO_CPL(s2) 1167 INT_L t1, CPU_INFO_IDEPTH(s2) # we need to inc. intr dept [all...] |
copy.S | 257 INT_L v0, 0(a0) # fetch int 379 INT_L v0, 0(a0) # fetch int 427 INT_L v0, (a0)
|
locore.S | 225 INT_L v1, CPU_INFO_CPL(v0) 482 INT_L t1, CPU_INFO_MTX_COUNT(t0) 716 INT_L a0, 0(a0) # a0 = coproc instruction
|
locore_mips3.S | 689 INT_L v0, (a0)
|
/src/sys/dev/arcbios/ |
arcbios_calls.S | 59 INT_L t9, 0(t9) 83 INT_L ta0, CALLFRAME2_SIZ+16(sp) # load 5th arg 84 INT_L ta1, CALLFRAME2_SIZ+20(sp) # load 6th arg 85 INT_L ta2, CALLFRAME2_SIZ+24(sp) # load 7th arg 86 INT_L ta3, CALLFRAME2_SIZ+28(sp) # load 8th arg 100 INT_L t9, 0(t9) 123 INT_L t9, __CONCAT(AFV_,name)(t9); \
|
/src/lib/libc/arch/riscv/sys/ |
cerror.S | 52 INT_L t0, CALLFRAME_S0(sp) # retrieve errno value
|
/src/lib/libc/compat/arch/mips/gen/ |
compat_sigsetjmp.S | 78 INT_L t1, _SC_MASK13(a0) # get "savemask"
|
compat_setjmp.S | 84 INT_L v1, CALLFRAME_SIZ+_STACK_T_FLAGS(sp)
|
/src/bin/ksh/ |
table.h | 55 #define INT_L BIT(20) /* long integer (no-op) */ 71 |LCASEV|UCASEV_AL|INT_U|INT_L)
|
c_ksh.c | 703 |INT_U|INT_L)) 706 |INT_U|INT_L);
|
/src/lib/libc/arch/mips/sys/ |
cerror.S | 70 INT_L t0, CALLFRAME_S0(sp)
|
/src/sys/arch/sgimips/stand/common/ |
start.S | 104 INT_L v0, SPB_FirmwareVector(v0) # FirmwareVector
|
/src/sys/arch/mips/rmi/ |
rmixl_spl.S | 115 INT_L v0, CPU_INFO_CPL(a3) ## get current IPL from cpu_info 201 INT_L v0, CPU_INFO_CPL(a3) ## old IPL for return value 308 INT_L t1, CPU_INFO_CPL(t0) # get current priority level
|
/src/lib/libc/arch/mips/gen/ |
setjmp.S | 83 INT_L v1, CALLFRAME_SIZ+_STACK_T_FLAGS(sp)
|
_setjmp.S | 145 INT_L v0, _SC_FPREGS_FCSR(a0)
|
/src/sys/arch/riscv/include/ |
asm.h | 194 #define INT_L lw
|
/src/sys/arch/mips/include/ |
asm.h | 485 #define INT_L lw 507 #define INT_L ld
|