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    Searched refs:INT_S (Results 1 - 24 of 24) sorted by relevancy

  /src/lib/libc/arch/mips/sys/
pipe.S 55 INT_S v0, 0(a0) # store the two file descriptors
56 INT_S v1, 4(a0)
ptrace.S 47 INT_S zero, _C_LABEL(errno) /* BOGUS */
cerror.S 56 INT_S v0, CALLFRAME_S0(sp) # save errno value
72 INT_S t0, 0(v0) # update errno value
85 INT_S v0, _C_LABEL(errno)
  /src/lib/libc/arch/riscv/sys/
cerror.S 48 INT_S a0, CALLFRAME_S0(sp) # save errno value
54 INT_S t0, 0(a0) # update errno value
58 INT_S a0, %lo(_C_LABEL(errno))(a1)
ptrace.S 59 INT_S zero, 0(a0)
70 INT_S zero, %lo(_C_LABEL(errno))(t0)
  /src/lib/libc/compat/arch/mips/sys/
compat_sigpending.S 54 INT_S v0, _SC_ONSTACK(a0)
compat_sigprocmask.S 60 INT_S v0, 0(a2) # store old mask
  /src/sys/dev/arcbios/
arcbios_calls.S 90 INT_S ta0, 16(sp) # save 5th arg on stack (o32)
91 INT_S ta1, 20(sp) # save 6th arg on stack (o32)
92 INT_S ta2, 24(sp) # save 7th arg on stack (o32)
93 INT_S ta3, 28(sp) # save 8th arg on stack (o32)
95 INT_S a4, 16(sp) # save 5th arg on stack (o32)
96 INT_S a5, 20(sp) # save 6th arg on stack (o32)
97 INT_S a6, 24(sp) # save 7th arg on stack (o32)
98 INT_S a7, 28(sp) # save 8th arg on stack (o32)
  /src/lib/libc/arch/mips/gen/
setjmp.S 86 INT_S v1, _SC_ONSTACK(a0) # save it in sc_onstack
115 INT_S zero, _SC_FPUSED(a0) # sc_fpused = 0
118 INT_S v0, _SC_FPUSED(a0) # sc_fpused = 1
120 INT_S v0, _SC_FPREGS_FCSR(a0)
_setjmp.S 111 INT_S v0, _SC_FPREGS_FCSR(a0)
  /src/lib/libc/compat/arch/mips/gen/
compat_sigsetjmp.S 64 INT_S a1, _SC_MASK13(a0) # save "savemask"
compat_setjmp.S 76 INT_S v0, _SC_MASK13(s0) # save sc_mask13
87 INT_S v1, _SC_ONSTACK(a0) # save it in sc_onstack
115 INT_S zero, _SC_FPUSED(a0) # sc_fpused = 0
118 INT_S v0, _SC_FPUSED(a0) # sc_fpused = 1
120 INT_S v0, _SC_FPREGS_FCSR(a0)
  /src/sys/arch/mips/mips/
lock_stubs_ras.S 141 INT_S a2, (a0) /* <- critical section end */
388 INT_S ta3, CPU_INFO_MTX_COUNT(t2)
392 INT_S v0, CPU_INFO_MTX_OLDSPL(t2) /* returned by splraise */
400 INT_S t1, MTX_LOCK(t0)
421 INT_S zero, MTX_LOCK(a0)
440 INT_S t0, CPU_INFO_MTX_COUNT(t2)
lock_stubs_llsc.S 255 INT_S ta3, CPU_INFO_MTX_COUNT(t2)
258 INT_S v0, CPU_INFO_MTX_OLDSPL(t2) /* returned by splraise */
297 INT_S zero, MTX_LOCK(a0)
314 INT_S t0, CPU_INFO_MTX_COUNT(t2)
spl.S 95 INT_S a1, CPU_INFO_CPL(a3) # save IPL in cpu_info
148 INT_S a0, CPU_INFO_CPL(a3) # save IPL in cpu_info (KSEG0)
190 INT_S zero, CPU_INFO_CPL(a3) # set ipl to 0
269 INT_S a1, CPU_INFO_CPL(a3) # save IPL in cpu_info
367 INT_S v1, (a0) # return a new pending mask
locore_mips1.S 282 INT_S t1, TF_BASE+TF_PPL(sp) # save priority level
463 INT_S s0, TF_BASE+TF_PPL(sp) # save priority level
500 INT_S t1, CPU_INFO_IDEPTH(s2) # store new interrupt depth
523 INT_S t1, CPU_INFO_IDEPTH(s2) # to it previous value
556 INT_S t0, CPU_INFO_SOFTINTS(s2) # and save it.
807 INT_S t1, CPU_INFO_IDEPTH(t0) # store new interrupt depth (1)
822 INT_S zero, CPU_INFO_IDEPTH(t0)
1223 INT_S zero, TLBMASK_MASK(a1)
locore.S 172 INT_S t0, _C_LABEL(mips_options)+MO_CPU_ID # save PRID register
173 INT_S t1, _C_LABEL(mips_options)+MO_FPU_ID # save FPU ID register
485 INT_S t1, CPU_INFO_MTX_COUNT(t0)
fp.S 85 #define FPX_S INT_S
768 INT_S v0, PCB_FPREGS+FRAME_FSR(t0)
1325 INT_S a2, PCB_FPREGS+FRAME_FSR(t1)
1405 INT_S a2, PCB_FPREGS+FRAME_FSR(t1)
2047 INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
2159 INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
2182 INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
2323 INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
2446 INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
2605 INT_S a2, PCB_FPREGS+FRAME_FSR(v0
    [all...]
copy.S 393 INT_S a1, 0(a0) # store word
mipsX_subr.S 790 INT_S t1, TF_BASE+TF_PPL(sp) # save priority level
1014 INT_S t1, TF_BASE+TF_PPL(sp) # save priority level
1134 INT_S s0, TF_BASE+TF_PPL(sp) # save priority level
1170 INT_S t1, CPU_INFO_IDEPTH(s2) # store new interrupt depth
1191 INT_S t1, CPU_INFO_IDEPTH(s2) # to it previous value
1227 INT_S t0, CPU_INFO_SOFTINTS(s2) # and save it.
1561 INT_S t1, CPU_INFO_IDEPTH(t0) # store new interrupt depth (1)
1575 INT_S zero, CPU_INFO_IDEPTH(t0)
2260 INT_S t2, TLBMASK_MASK(a1)
  /src/sys/arch/riscv/riscv/
spl.S 69 INT_S a0, CI_CPL(a3) // change IPL
93 INT_S zero, CI_CPL(a3) // set current IPL to IPL_NONE
196 INT_S t1, CI_CPL(a3) // change IPL
cpu_switch.S 137 // INT_S t1, CI_MTX_COUNT(t0) // save it
443 INT_S zero, L_MD_ASTPENDING(tp)
  /src/sys/arch/riscv/include/
asm.h 196 #define INT_S sw
  /src/sys/arch/mips/include/
asm.h 487 #define INT_S sw
509 #define INT_S sd

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