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    Searched refs:IO_ICU1 (Results 1 - 22 of 22) sorted by relevancy

  /src/sys/arch/arm/footbridge/isa/
icu.h 53 outb(IO_ICU1 + 1, imen); \
isa_machdep.c 125 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
126 outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */
127 outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
129 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
131 outb(IO_ICU1+1, 1); /* 8086 mode */
133 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
134 outb(IO_ICU1, 0x68); /* special mask mode (if available) */
135 outb(IO_ICU1, 0x0a); /* Read IRR by default. */
137 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
  /src/sys/arch/shark/isa/
icu.h 53 outb(IO_ICU1 + 1, imen); \
isa_shark_machdep.c 124 outb(IO_ICU1, 0x19); /* reset; four bytes, level triggered */
125 outb(IO_ICU1+1, ICU_OFFSET); /* int base: not used */
126 outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
127 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
128 outb(IO_ICU1+1, 0xff); /* disable all interrupts */
129 outb(IO_ICU1, 0x68); /* special mask mode (if available) */
130 outb(IO_ICU1, 0x0a); /* Read IRR, not ISR */
isa_irq.S 136 ldrb r8, [r0, #IO_ICU1] /* ocw3 = irr */
365 strbne r1, [r0, #(IO_ICU1 + 1)] /* icu1 / ocw1 */
  /src/sys/arch/powerpc/pic/
i8259_common.c 51 isa_outb(IO_ICU1, 0x11); /* program device, four bytes */
52 isa_outb(IO_ICU1+1, 0); /* starting at this vector */
53 isa_outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
54 isa_outb(IO_ICU1+1, 1); /* 8086 mode */
55 isa_outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
74 isa_outb(IO_ICU1+1, i8259->enable_mask);
85 isa_outb(IO_ICU1+1, i8259->enable_mask);
93 isa_outb(IO_ICU1, 0xe0 | irq);
96 isa_outb(IO_ICU1, 0xe0 | IRQ_SLAVE);
105 isa_outb(IO_ICU1, 0x0c)
    [all...]
  /src/sys/arch/ofppc/isa/
isa_machdep.c 61 err = bus_space_map(&genppc_isa_io_space_tag, IO_ICU1, 2, 0,
64 panic("Can't map IO_ICU1 error %d\n", err);
82 if (addr == IO_ICU1 || addr == IO_ICU1+1)
84 addr-IO_ICU1);
97 if (addr == IO_ICU1 || addr == IO_ICU1+1)
99 addr-IO_ICU1, val);
  /src/sys/arch/x86/x86/
i8259.c 133 outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_LTIM | ICW1_IC4);
137 outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);
140 outb(IO_ICU1 + PIC_ICW2, ICU_OFFSET);
142 outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE));
146 outb(IO_ICU1 + PIC_ICW4, ICW4_AEOI | ICW4_8086);
149 outb(IO_ICU1 + PIC_ICW4, ICW4_8086);
152 outb(IO_ICU1 + PIC_OCW1, 0xff);
154 outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);
156 outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR);
159 outb(IO_ICU1 + PIC_OCW2, OCW2_SELECT | OCW2_R | OCW2_SL
    [all...]
  /src/sys/arch/evbmips/loongson/
isa_machdep.c 64 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + 1) = imr1;
84 (void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + 1);
85 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + 1) =
88 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW2) =
yeeloong_machdep.c 286 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1) = 0xff;
287 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW1) =
289 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW2) = ICW2_VECTOR(0);
290 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW3) = ICW3_CASCADE(2);
291 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW4) = ICW4_8086;
294 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1) = 0xff;
297 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;
298 (void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3);
483 imr1 = 0xff & ~REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1);
495 isr1 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU1);
    [all...]
generic2e_machdep.c 296 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) =
298 ocw1 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3);
563 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW1) =
565 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW2) = ICW2_VECTOR(0);
566 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW3) = ICW3_CASCADE(2);
567 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW4) = ICW4_8086;
569 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1) = 0xff;
571 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) =
574 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;
  /src/sys/arch/x86/include/
i8259.h 50 #define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
92 outb %al,$IO_ICU1
103 outb %al,$IO_ICU1
113 outb %al,$IO_ICU1
  /src/sys/arch/arc/isa/
isabus.c 311 isa_outb(IO_ICU1 + PIC_OCW1, imen);
433 isa_outb(IO_ICU1,
436 isa_inb(IO_ICU1 + PIC_OCW1);
437 isa_outb(IO_ICU1 + PIC_OCW1, imen);
438 isa_outb(IO_ICU1 + PIC_OCW2,
456 isa_inb(IO_ICU1 + PIC_OCW1);
458 isa_outb(IO_ICU1 + PIC_OCW1, imen);
487 isa_outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);
489 isa_outb(IO_ICU1 + PIC_ICW2, 0);
491 isa_outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE))
    [all...]
  /src/sys/arch/arc/arc/
c_isa.c 184 isa_outb(IO_ICU1, 0x0f); /* Poll */
185 vector = isa_inb(IO_ICU1);
  /src/sys/dev/isa/
isareg.h 50 #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */
  /src/sys/arch/alpha/jensenio/
jensenio_intr.c 375 static const int picaddr[2] = { IO_ICU1, IO_ICU2 };
  /src/sys/arch/cobalt/cobalt/
interrupt.c 178 bus_space_map(icu_bst, PCIB_BASE + IO_ICU1, IO_ICUSIZE, 0, &icu1_bsh);
  /src/sys/arch/alpha/pci/
sio_pic.c 347 if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) ||
  /src/sys/arch/algor/pci/
pcib.c 168 if (bus_space_map(sc->sc_iot, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
  /src/sys/arch/evbmips/malta/pci/
pcib.c 210 if (bus_space_map(sc->sc_iot, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
  /src/sys/arch/amd64/amd64/
vector.S 447 #define ICUADDR IO_ICU1
  /src/sys/arch/i386/i386/
vector.S 460 #define ICUADDR IO_ICU1

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