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    Searched refs:IO_ICU2 (Results 1 - 22 of 22) sorted by relevancy

  /src/sys/arch/arm/footbridge/isa/
icu.h 54 outb(IO_ICU2 + 1, imen >> 8); \
isa_machdep.c 140 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
141 outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */
142 outb(IO_ICU2+1, IRQ_SLAVE);
144 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
146 outb(IO_ICU2+1, 1); /* 8086 mode */
148 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
149 outb(IO_ICU2, 0x68); /* special mask mode (if available) */
150 outb(IO_ICU2, 0x0a); /* Read IRR by default. */
  /src/sys/arch/shark/isa/
icu.h 54 outb(IO_ICU2 + 1, imen >> 8); \
isa_shark_machdep.c 132 outb(IO_ICU2, 0x19); /* reset; four bytes, level triggered */
133 outb(IO_ICU2+1, ICU_OFFSET+8); /* int base + offset for master: not used */
134 outb(IO_ICU2+1, IRQ_SLAVE); /* who ami i? */
135 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
136 outb(IO_ICU2+1, 0xff); /* disable all interrupts */
137 outb(IO_ICU2, 0x68); /* special mask mode (if available) */
138 outb(IO_ICU2, 0x0a); /* Read IRR by default. */
isa_irq.S 146 ldrbne r1, [r0, #IO_ICU2] /* ocw3 = irr */
370 strbne r1, [r0, #(IO_ICU2 + 1)] /* icu2 / ocw1 */
  /src/sys/arch/powerpc/pic/
i8259_common.c 57 isa_outb(IO_ICU2, 0x11); /* program device, four bytes */
58 isa_outb(IO_ICU2+1, 8); /* starting at this vector */
59 isa_outb(IO_ICU2+1, IRQ_SLAVE);
60 isa_outb(IO_ICU2+1, 1); /* 8086 mode */
61 isa_outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
75 isa_outb(IO_ICU2+1, i8259->enable_mask >> 8);
86 isa_outb(IO_ICU2+1, i8259->enable_mask >> 8);
95 isa_outb(IO_ICU2, 0xe0 | (irq & 7));
108 isa_outb(IO_ICU2, 0x0c);
109 irq = (isa_inb(IO_ICU2) & 0x07) + 8
    [all...]
  /src/sys/arch/ofppc/isa/
isa_machdep.c 66 err = bus_space_map(&genppc_isa_io_space_tag, IO_ICU2, 2, 0,
69 panic("Can't map IO_ICU2 error %d\n", err);
85 if (addr == IO_ICU2 || addr == IO_ICU2+1)
87 addr-IO_ICU2);
100 if (addr == IO_ICU2 || addr == IO_ICU2+1)
102 addr-IO_ICU2, val);
  /src/sys/arch/x86/x86/
i8259.c 167 outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_LTIM | ICW1_IC4);
171 outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);
174 outb(IO_ICU2 + PIC_ICW2, ICU_OFFSET + 8);
176 outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE));
179 outb(IO_ICU2 + PIC_ICW4, ICW4_AEOI | ICW4_8086);
182 outb(IO_ICU2 + PIC_ICW4, ICW4_8086);
185 outb(IO_ICU2 + PIC_OCW1, 0xff);
187 outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);
189 outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR);
203 port = IO_ICU2 + PIC_OCW1
    [all...]
  /src/sys/arch/evbmips/loongson/
isa_machdep.c 62 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) = imr2;
75 (void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1);
76 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) =
79 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW2) =
yeeloong_machdep.c 301 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff;
302 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW1) =
304 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8);
305 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(2);
306 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086;
309 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff;
311 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;
312 (void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3);
485 imr2 = 0xff & ~REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1);
497 isr2 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU2);
    [all...]
generic2e_machdep.c 305 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) =
307 ocw2 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3);
577 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW1) =
579 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8);
580 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(2);
581 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086;
583 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff;
585 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) =
588 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;
  /src/sys/arch/arc/isa/
isabus.c 312 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8);
428 isa_inb(IO_ICU2 + PIC_OCW1);
429 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8);
430 isa_outb(IO_ICU2 + PIC_OCW2,
457 isa_inb(IO_ICU2 + PIC_OCW1);
459 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8);
509 isa_outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);
511 isa_outb(IO_ICU2 + PIC_ICW2, 8);
513 isa_outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE));
515 isa_outb(IO_ICU2 + PIC_ICW4, ICW4_8086);
    [all...]
  /src/sys/arch/arc/arc/
c_isa.c 188 isa_outb(IO_ICU2, 0x0f);
189 vector = isa_inb(IO_ICU2);
  /src/sys/arch/x86/include/
i8259.h 50 #define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
111 outb %al,$IO_ICU2 /* do the second ICU first */ ;\
  /src/sys/dev/isa/
isareg.h 59 #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */
  /src/sys/arch/alpha/jensenio/
jensenio_intr.c 375 static const int picaddr[2] = { IO_ICU1, IO_ICU2 };
  /src/sys/arch/cobalt/cobalt/
interrupt.c 179 bus_space_map(icu_bst, PCIB_BASE + IO_ICU2, IO_ICUSIZE, 0, &icu2_bsh);
  /src/sys/arch/alpha/pci/
sio_pic.c 348 bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2))
  /src/sys/arch/algor/pci/
pcib.c 170 if (bus_space_map(sc->sc_iot, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
  /src/sys/arch/evbmips/malta/pci/
pcib.c 212 if (bus_space_map(sc->sc_iot, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
  /src/sys/arch/amd64/amd64/
vector.S 466 #define ICUADDR IO_ICU2
  /src/sys/arch/i386/i386/
vector.S 479 #define ICUADDR IO_ICU2

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