| /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/ |
| ExecuteStage.cpp | 43 bool ExecuteStage::isAvailable(const InstRef &IR) const {
44 if (Scheduler::Status S = HWS.isAvailable(IR)) {
46 notifyEvent<HWStallEvent>(HWStallEvent(ET, IR));
53 Error ExecuteStage::issueInstruction(InstRef &IR) {
58 HWS.issueInstruction(IR, Used, Pending, Ready);
59 Instruction &IS = *IR.getInstruction();
62 notifyReservedOrReleasedBuffers(IR, /* Reserved */ false);
64 notifyInstructionIssued(IR, Used);
66 notifyInstructionExecuted(IR);
68 if (Error S = moveToTheNextStage(IR))
[all...] |
| DispatchStage.cpp | 38 void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
41 LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: #" << IR << '\n');
43 HWInstructionDispatchedEvent(IR, UsedRegs, UOps));
46 bool DispatchStage::checkPRF(const InstRef &IR) const {
48 for (const WriteState &RegDef : IR.getInstruction()->getDefs())
55 HWStallEvent(HWStallEvent::RegisterFileStall, IR));
62 bool DispatchStage::checkRCU(const InstRef &IR) const {
63 const unsigned NumMicroOps = IR.getInstruction()->getNumMicroOps();
67 HWStallEvent(HWStallEvent::RetireControlUnitStall, IR));
71 bool DispatchStage::canDispatch(const InstRef &IR) const
[all...] |
| InOrderIssueStage.cpp | 35 bool InOrderIssueStage::isAvailable(const InstRef &IR) const {
39 const Instruction &Inst = *IR.getInstruction();
55 static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) {
56 if (RM.checkAvailability(IR.getInstruction()->getDesc())) {
57 LLVM_DEBUG(dbgs() << "[E] Stall #" << IR << '\n');
64 static unsigned findLastWriteBackCycle(const InstRef &IR) {
66 for (const WriteState &WS : IR.getInstruction()->getDefs()) {
77 static unsigned findFirstWriteBackCycle(const InstRef &IR) {
79 for (const WriteState &WS : IR.getInstruction()->getDefs()) {
95 const InstRef &IR) {
[all...] |
| MicroOpQueueStage.cpp | 22 InstRef IR = Buffer[CurrentInstructionSlotIdx];
23 while (IR && checkNextStage(IR)) {
24 if (llvm::Error Val = moveToTheNextStage(IR))
28 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);
32 IR = Buffer[CurrentInstructionSlotIdx];
46 Error MicroOpQueueStage::execute(InstRef &IR) {
47 Buffer[NextAvailableSlotIdx] = IR;
48 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);
|
| RetireStage.cpp | 36 notifyInstructionRetired(Current.IR);
49 llvm::Error RetireStage::execute(InstRef &IR) {
50 Instruction &IS = *IR.getInstruction();
60 void RetireStage::notifyInstructionRetired(const InstRef &IR) const {
61 LLVM_DEBUG(llvm::dbgs() << "[E] Instruction Retired: #" << IR << '\n');
63 const Instruction &Inst = *IR.getInstruction();
67 LSU.onInstructionRetired(IR);
71 notifyEvent<HWInstructionEvent>(HWInstructionRetiredEvent(IR, FreedRegs));
|
| /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/ |
| Scheduler.cpp | 40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) {
42 Resources->canBeDispatched(IR.getInstruction()->getUsedBuffers());
55 LSUnit::Status LSS = LSU.isAvailable(IR);
71 InstRef &IR,
73 Instruction *IS = IR.getInstruction();
82 IS->execute(IR.getSourceIndex());
87 LSU.onInstructionIssued(IR);
93 IssuedSet.emplace_back(IR);
95 LSU.onInstructionExecuted(IR);
100 InstRef &IR,
[all...] |
| RetireControlUnit.cpp | 43 unsigned RetireControlUnit::dispatch(const InstRef &IR) {
44 const Instruction &Inst = *IR.getInstruction();
49 Queue[NextAvailableSlotIdx] = {IR, Entries, false};
61 const Instruction *Inst = Current.IR.getInstruction();
79 Current.IR.getInstruction()->retire();
90 assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!");
|
| LSUnit.cpp | 69 unsigned LSUnit::dispatch(const InstRef &IR) {
70 const InstrDesc &Desc = IR.getInstruction()->getDesc();
195 LSUnit::Status LSUnit::isAvailable(const InstRef &IR) const {
196 const InstrDesc &Desc = IR.getInstruction()->getDesc();
204 void LSUnitBase::onInstructionExecuted(const InstRef &IR) {
205 unsigned GroupID = IR.getInstruction()->getLSUTokenID();
208 It->second->onInstructionExecuted(IR);
213 void LSUnitBase::onInstructionRetired(const InstRef &IR) {
214 const InstrDesc &Desc = IR.getInstruction()->getDesc();
221 LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << IR.getSourceIndex(
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/ |
| DispatchStage.h | 58 bool checkRCU(const InstRef &IR) const;
59 bool checkPRF(const InstRef &IR) const;
60 bool canDispatch(const InstRef &IR) const;
61 Error dispatch(InstRef IR);
63 void notifyInstructionDispatched(const InstRef &IR,
72 bool isAvailable(const InstRef &IR) const override;
78 Error execute(InstRef &IR) override;
|
| ExecuteStage.h | 37 Error issueInstruction(InstRef &IR);
44 Error handleInstructionEliminated(InstRef &IR);
62 bool isAvailable(const InstRef &IR) const override;
73 Error execute(InstRef &IR) override;
76 const InstRef &IR,
78 void notifyInstructionExecuted(const InstRef &IR) const;
79 void notifyInstructionPending(const InstRef &IR) const;
80 void notifyInstructionReady(const InstRef &IR) const;
84 void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
|
| MicroOpQueueStage.h | 54 unsigned getNormalizedOpcodes(const InstRef &IR) const {
57 IR.getInstruction()->getDesc().NumMicroOps);
67 bool isAvailable(const InstRef &IR) const override {
70 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);
80 Error execute(InstRef &IR) override;
|
| Stage.h | 41 /// Returns true if it can execute IR during this cycle.
42 virtual bool isAvailable(const InstRef &IR) const { return true; }
54 /// The primary action that this stage performs on instruction IR.
55 virtual Error execute(InstRef &IR) = 0;
62 bool checkNextStage(const InstRef &IR) const {
63 return NextInSequence && NextInSequence->isAvailable(IR);
70 Error moveToTheNextStage(InstRef &IR) {
71 assert(checkNextStage(IR) && "Next stage is not ready!");
72 return NextInSequence->execute(IR);
|
| EntryStage.h | 41 bool isAvailable(const InstRef &IR) const override;
43 Error execute(InstRef &IR) override;
|
| InOrderIssueStage.h | 64 /// If IR has an unmet register or resource dependency, canExecute returns
67 bool canExecute(const InstRef &IR, unsigned *StallCycles) const;
69 /// Issue the instruction, or update StallCycles if IR is stalled.
70 Error tryIssue(InstRef &IR, unsigned *StallCycles);
79 void retireInstruction(InstRef &IR);
90 Error execute(InstRef &IR) override;
|
| /src/external/gpl3/gcc.old/dist/libphobos/src/std/regex/internal/ |
| generator.d | 18 import std.regex.internal.ir : Regex, IR, IRL;
47 switch (re.ir[pc].code)
49 case IR.Char:
50 formattedWrite(app,"%s", cast(dchar) re.ir[pc].data);
51 pc += IRL!(IR.Char);
53 case IR.OrChar:
54 uint len = re.ir[pc].sequence;
55 formattedWrite(app, "%s", cast(dchar) re.ir[pc + rand(len)].data);
58 case IR.CodepointSet
[all...] |
| parser.d | 7 import std.regex.internal.ir;
23 ir = g.ir;
103 if (code[pc].code == IR.GotoEndOr)
114 if (code[pc].code == IR.LookbehindStart
115 || code[pc].code == IR.NeglookbehindStart)
128 if (code[pc].code == IR.OrStart)
133 uint i = pc + IRL!(IR.OrStart);
134 while (code[i].code == IR.Option)
136 if (code[i - 1].code != IR.OrStart
[all...] |
| backtracking.d | 10 import std.regex.internal.ir;
342 pc, counter, disassemble(re.ir, pc, re.dict),
344 switch (re.ir[pc].code)
346 case IR.OrChar://assumes IRL!(OrChar) == 1
349 uint len = re.ir[pc].sequence;
351 if (re.ir[pc].data != front && re.ir[pc+1].data != front)
354 if (re.ir[pc].data == front)
362 case IR.Char:
363 if (atEnd || front != re.ir[pc].data
[all...] |
| thompson.d | 14 import std.regex.internal.ir;
92 static bool op(IR code:IR.End)(E e, S* state)
96 finish(t, matches, re.ir[t.pc].data);
108 static bool op(IR code:IR.Wordboundary)(E e, S* state)
117 t.pc += IRL!(IR.Wordboundary);
123 t.pc += IRL!(IR.Wordboundary);
132 t.pc += IRL!(IR.Wordboundary);
140 static bool op(IR code:IR.Notwordboundary)(E e, S* state
[all...] |
| kickstart.d | 10 import std.regex.internal.ir;
152 switch (re.ir[i].code)
154 case IR.Char:
155 fChar = re.ir[i].data;
164 case IR.GroupStart, IR.GroupEnd:
165 i += IRL!(IR.GroupStart);
167 case IR.Bof, IR.Bol, IR.Wordboundary, IR.Notwordboundary
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| PassManagerImpl.h | 10 /// methods. These classes should be explicitly instantiated for any IR unit,
18 #include "llvm/IR/PassManager.h"
36 AnalysisManager<IRUnitT, ExtraArgTs...>::clear(IRUnitT &IR,
38 if (auto *PI = getCachedResult<PassInstrumentationAnalysis>(IR))
41 auto ResultsListI = AnalysisResultLists.find(&IR);
46 AnalysisResults.erase({IDAndResult.first, &IR});
48 // And actually destroy and erase the results associated with this IR.
55 AnalysisKey *ID, IRUnitT &IR, ExtraArgTs... ExtraArgs) {
59 std::make_pair(ID, &IR), typename AnalysisResultListT::iterator()));
68 PI = getResult<PassInstrumentationAnalysis>(IR, ExtraArgs...)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/ |
| LSUnit.h | 115 void onGroupIssued(const InstRef &IR, bool ShouldUpdateCriticalDep) {
122 unsigned Cycles = IR.getInstruction()->getCyclesLeft();
124 CriticalPredecessor.IID = IR.getSourceIndex();
135 void onInstructionIssued(const InstRef &IR) {
140 const Instruction &IS = *IR.getInstruction();
144 CriticalMemoryInstruction = IR;
146 CriticalMemoryInstruction = IR;
163 void onInstructionExecuted(const InstRef &IR) {
169 CriticalMemoryInstruction.getSourceIndex() == IR.getSourceIndex()) {
254 /// accomodate instruction IR. By default, LSU_AVAILABLE is returned if IR i
[all...] |
| Scheduler.h | 138 InstRef &IR,
181 /// Check if the instruction in 'IR' can be dispatched during this cycle.
185 /// IR cannot be dispatched to the Scheduler due to unavailable resources.
186 Status isAvailable(const InstRef &IR);
191 /// Returns true if instruction IR is ready to be issued to the underlying
193 /// previous call to method `isAvailable(IR)` returned `SC_AVAILABLE`.
195 /// If IR is a memory operation, then the Scheduler queries the LS unit to
198 bool dispatch(InstRef &IR);
204 InstRef &IR,
209 /// Returns true if IR has to be issued immediately, or if IR is a zer
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Passes/ |
| StandardInstrumentations.cpp | 10 /// This file defines IR-printing pass instrumentation callbacks as well as
22 #include "llvm/IR/Function.h"
23 #include "llvm/IR/LegacyPassManager.h"
24 #include "llvm/IR/Module.h"
25 #include "llvm/IR/PassInstrumentation.h"
26 #include "llvm/IR/PassManager.h"
27 #include "llvm/IR/PrintPasses.h"
28 #include "llvm/IR/Verifier.h"
48 // An option that prints out the IR after passes, similar to
49 // -print-after-all except that it only prints the IR after passes tha
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| HWEventListener.h | 53 : Type(type), IR(Inst) {}
59 const InstRef &IR;
65 HWInstructionIssuedEvent(const InstRef &IR,
67 : HWInstructionEvent(HWInstructionEvent::Issued, IR), UsedResources(UR) {}
74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs,
76 : HWInstructionEvent(HWInstructionEvent::Dispatched, IR),
83 // the instruction descriptor of IR.
84 // The only exception is when IR declares a number of micro opcodes
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs)
96 : HWInstructionEvent(HWInstructionEvent::Retired, IR),
[all...] |
| /src/external/apache2/llvm/bin/llvm-dis/ |
| Makefile | 16 IR \
|
