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    Searched refs:IS_FPGA_MAXIMUS_DC (Results 1 - 25 of 26) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
amdgpu_hw_translate.c 68 if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
amdgpu_hw_factory.c 70 if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
amdgpu_rv1_clk_mgr_vbios_smu.c 108 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_hw_sequencer.c 128 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr_vbios_smu.c 99 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
amdgpu_rn_clk_mgr.c 723 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
758 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_init.c 134 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
amdgpu_dcn20_dsc.c 725 if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) {
amdgpu_dcn20_hwseq.c 2023 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_init.c 143 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
amdgpu_dcn21_resource.c 1361 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment))
1410 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
1677 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1905 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
amdgpu_dce112_clk_mgr.c 118 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
160 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_hwss.c 406 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
455 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
480 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
545 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
554 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
amdgpu_dc_link.c 2948 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
2991 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3074 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3088 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
amdgpu_dc_link_dp.c 4095 IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
4131 IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_hw_sequencer.c 167 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_types.h 74 #define IS_FPGA_MAXIMUS_DC(dce_environment) \
78 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
amdgpu_dc_helper.c 519 !IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
531 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
amdgpu_dcn20_clk_mgr.c 456 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_dmcu.c 881 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
amdgpu_dce_clock_source.c 914 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
dce_clk_mgr.c 334 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 875 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1255 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1284 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2654 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2687 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
amdgpu_dcn10_resource.c 1586 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 210 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))

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