1 /* $NetBSD: if_iwmreg.h,v 1.15 2025/12/01 16:02:42 mlelstv Exp $ */ 2 /* OpenBSD: if_iwmreg.h,v 1.19 2016/09/20 11:46:09 stsp Exp */ 3 4 /*- 5 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 6 * which were used as the reference documentation for this implementation. 7 * 8 *********************************************************************** 9 * 10 * This file is provided under a dual BSD/GPLv2 license. When using or 11 * redistributing this file, you may do so under either license. 12 * 13 * GPL LICENSE SUMMARY 14 * 15 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 16 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 17 * Copyright(c) 2016 Intel Deutschland GmbH 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of version 2 of the GNU General Public License as 21 * published by the Free Software Foundation. 22 * 23 * This program is distributed in the hope that it will be useful, but 24 * WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 26 * General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 31 * USA 32 * 33 * The full GNU General Public License is included in this distribution 34 * in the file called COPYING. 35 * 36 * Contact Information: 37 * Intel Linux Wireless <linuxwifi (at) intel.com> 38 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 39 * 40 * BSD LICENSE 41 * 42 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 43 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 44 * Copyright(c) 2016 Intel Deutschland GmbH 45 * All rights reserved. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 51 * * Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * * Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in 55 * the documentation and/or other materials provided with the 56 * distribution. 57 * * Neither the name Intel Corporation nor the names of its 58 * contributors may be used to endorse or promote products derived 59 * from this software without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 62 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 63 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 64 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 65 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 66 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 67 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 68 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 69 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 70 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 72 */ 73 74 /* 75 * CSR (control and status registers) 76 * 77 * CSR registers are mapped directly into PCI bus space, and are accessible 78 * whenever platform supplies power to device, even when device is in 79 * low power states due to driver-invoked device resets 80 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 81 * 82 * Use iwl_write32() and iwl_read32() family to access these registers; 83 * these provide simple PCI bus access, without waking up the MAC. 84 * Do not use iwl_write_direct32() family for these registers; 85 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 86 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 87 * the CSR registers. 88 * 89 * NOTE: Device does need to be awake in order to read this memory 90 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 91 */ 92 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 93 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 94 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 95 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 96 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 97 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 98 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 99 #define IWM_CSR_GP_CNTRL (0x024) 100 101 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 102 #define IWM_CSR_INT_PERIODIC_REG (0x005) 103 104 /* 105 * Hardware revision info 106 * Bit fields: 107 * 31-16: Reserved 108 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 109 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 110 * 1-0: "Dash" (-) value, as in A-1, etc. 111 */ 112 #define IWM_CSR_HW_REV (0x028) 113 114 /* 115 * EEPROM and OTP (one-time-programmable) memory reads 116 * 117 * NOTE: Device must be awake, initialized via apm_ops.init(), 118 * in order to read. 119 */ 120 #define IWM_CSR_EEPROM_REG (0x02c) 121 #define IWM_CSR_EEPROM_GP (0x030) 122 #define IWM_CSR_OTP_GP_REG (0x034) 123 124 #define IWM_CSR_GIO_REG (0x03C) 125 #define IWM_CSR_GP_UCODE_REG (0x048) 126 #define IWM_CSR_GP_DRIVER_REG (0x050) 127 128 /* 129 * UCODE-DRIVER GP (general purpose) mailbox registers. 130 * SET/CLR registers set/clear bit(s) if "1" is written. 131 */ 132 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 133 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 134 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 135 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 136 137 #define IWM_CSR_MBOX_SET_REG (0x088) 138 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 139 140 #define IWM_CSR_LED_REG (0x094) 141 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 142 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 143 144 145 /* GIO Chicken Bits (PCI Express bus link power management) */ 146 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 147 148 /* Analog phase-lock-loop configuration */ 149 #define IWM_CSR_ANA_PLL_CFG (0x20c) 150 151 /* 152 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 153 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 154 * See also IWM_CSR_HW_REV register. 155 * Bit fields: 156 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 157 * 1-0: "Dash" (-) value, as in C-1, etc. 158 */ 159 #define IWM_CSR_HW_REV_WA_REG (0x22C) 160 161 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 162 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 163 164 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 166 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 168 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 169 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 171 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 173 174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 180 181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 185 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 186 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 187 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 188 189 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 190 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 191 192 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 193 * acknowledged (reset) by host writing "1" to flagged bits. */ 194 #define IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 195 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 196 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 197 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 198 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 199 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 200 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 201 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 202 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 203 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 204 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 205 206 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 207 IWM_CSR_INT_BIT_HW_ERR | \ 208 IWM_CSR_INT_BIT_FH_TX | \ 209 IWM_CSR_INT_BIT_SW_ERR | \ 210 IWM_CSR_INT_BIT_RF_KILL | \ 211 IWM_CSR_INT_BIT_SW_RX | \ 212 IWM_CSR_INT_BIT_WAKEUP | \ 213 IWM_CSR_INT_BIT_ALIVE | \ 214 IWM_CSR_INT_BIT_RX_PERIODIC) 215 216 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 217 #define IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ 218 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 219 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 220 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 221 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 222 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 223 224 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 225 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 226 IWM_CSR_FH_INT_BIT_RX_CHNL0) 227 228 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 229 IWM_CSR_FH_INT_BIT_TX_CHNL0) 230 231 /* GPIO */ 232 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 233 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 234 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 235 236 /* RESET */ 237 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 238 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 239 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 240 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 241 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 242 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 243 244 /* 245 * GP (general purpose) CONTROL REGISTER 246 * Bit fields: 247 * 27: HW_RF_KILL_SW 248 * Indicates state of (platform's) hardware RF-Kill switch 249 * 26-24: POWER_SAVE_TYPE 250 * Indicates current power-saving mode: 251 * 000 -- No power saving 252 * 001 -- MAC power-down 253 * 010 -- PHY (radio) power-down 254 * 011 -- Error 255 * 9-6: SYS_CONFIG 256 * Indicates current system configuration, reflecting pins on chip 257 * as forced high/low by device circuit board. 258 * 4: GOING_TO_SLEEP 259 * Indicates MAC is entering a power-saving sleep power-down. 260 * Not a good time to access device-internal resources. 261 * 3: MAC_ACCESS_REQ 262 * Host sets this to request and maintain MAC wakeup, to allow host 263 * access to device-internal resources. Host must wait for 264 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 265 * device registers. 266 * 2: INIT_DONE 267 * Host sets this to put device into fully operational D0 power mode. 268 * Host resets this after SW_RESET to put device into low power mode. 269 * 0: MAC_CLOCK_READY 270 * Indicates MAC (ucode processor, etc.) is powered up and can run. 271 * Internal resources are accessible. 272 * NOTE: This does not indicate that the processor is actually running. 273 * NOTE: This does not indicate that device has completed 274 * init or post-power-down restore of internal SRAM memory. 275 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 276 * SRAM is restored and uCode is in normal operation mode. 277 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 278 * do not need to save/restore it. 279 * NOTE: After device reset, this bit remains "0" until host sets 280 * INIT_DONE 281 */ 282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 283 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 285 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 286 287 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 288 289 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 290 #define IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 291 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 292 293 294 /* HW REV */ 295 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 296 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 297 298 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 299 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 300 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 301 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 302 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 303 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 304 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 305 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 306 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 307 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 308 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 309 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 310 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 311 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 312 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 313 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 314 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 315 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 316 317 /* EEPROM REG */ 318 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 319 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 320 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 321 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 322 323 /* EEPROM GP */ 324 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 325 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 326 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 327 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 328 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 329 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 330 331 /* One-time-programmable memory general purpose reg */ 332 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 333 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 334 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 335 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 336 337 /* GP REG */ 338 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 339 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 340 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 341 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 342 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 343 344 345 /* CSR GIO */ 346 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 347 348 /* 349 * UCODE-DRIVER GP (general purpose) mailbox register 1 350 * Host driver and uCode write and/or read this register to communicate with 351 * each other. 352 * Bit fields: 353 * 4: UCODE_DISABLE 354 * Host sets this to request permanent halt of uCode, same as 355 * sending CARD_STATE command with "halt" bit set. 356 * 3: CT_KILL_EXIT 357 * Host sets this to request exit from CT_KILL state, i.e. host thinks 358 * device temperature is low enough to continue normal operation. 359 * 2: CMD_BLOCKED 360 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 361 * to release uCode to clear all Tx and command queues, enter 362 * unassociated mode, and power down. 363 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 364 * 1: SW_BIT_RFKILL 365 * Host sets this when issuing CARD_STATE command to request 366 * device sleep. 367 * 0: MAC_SLEEP 368 * uCode sets this when preparing a power-saving power-down. 369 * uCode resets this when power-up is complete and SRAM is sane. 370 * NOTE: device saves internal SRAM data to host when powering down, 371 * and must restore this data after powering back up. 372 * MAC_SLEEP is the best indication that restore is complete. 373 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 374 * do not need to save/restore it. 375 */ 376 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 377 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 378 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 379 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 380 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 381 382 /* GP Driver */ 383 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 384 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 385 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 386 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 387 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 388 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 389 390 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 391 392 /* GIO Chicken Bits (PCI Express bus link power management) */ 393 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 394 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 395 396 /* LED */ 397 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 398 #define IWM_CSR_LED_REG_TURN_ON (0x60) 399 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 400 401 /* ANA_PLL */ 402 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 403 404 /* HPET MEM debug */ 405 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 406 407 /* DRAM INT TABLE */ 408 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31) 409 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 410 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 411 412 /* SECURE boot registers */ 413 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 414 enum iwm_secure_boot_config_reg { 415 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 416 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 417 }; 418 419 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 420 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 421 enum iwm_secure_boot_status_reg { 422 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 423 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 424 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 425 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 426 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 427 }; 428 429 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 430 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 431 enum iwm_secure_load_status_reg { 432 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 433 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 434 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 435 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 436 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 437 }; 438 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 439 440 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 441 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 442 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 443 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 444 445 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 446 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 447 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 448 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 449 450 #define IWM_CSR_SECURE_TIME_OUT (100) 451 452 /* extended range in FW SRAM */ 453 #define IWM_FW_MEM_EXTENDED_START 0x40000 454 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 455 456 /* FW chicken bits */ 457 #define IWM_LMPM_CHICK 0xa01ff8 458 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 459 460 #define IWM_FH_TCSR_0_REG0 (0x1D00) 461 462 /* 463 * HBUS (Host-side Bus) 464 * 465 * HBUS registers are mapped directly into PCI bus space, but are used 466 * to indirectly access device's internal memory or registers that 467 * may be powered-down. 468 * 469 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 470 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 471 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 472 * internal resources. 473 * 474 * Do not use iwl_write32()/iwl_read32() family to access these registers; 475 * these provide only simple PCI bus access, without waking up the MAC. 476 */ 477 #define IWM_HBUS_BASE (0x400) 478 479 /* 480 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 481 * structures, error log, event log, verifying uCode load). 482 * First write to address register, then read from or write to data register 483 * to complete the job. Once the address register is set up, accesses to 484 * data registers auto-increment the address by one dword. 485 * Bit usage for address registers (read or write): 486 * 0-31: memory address within device 487 */ 488 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 489 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 490 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 491 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 492 493 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 494 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 495 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 496 497 /* 498 * Registers for accessing device's internal peripheral registers 499 * (e.g. SCD, BSM, etc.). First write to address register, 500 * then read from or write to data register to complete the job. 501 * Bit usage for address registers (read or write): 502 * 0-15: register address (offset) within device 503 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 504 */ 505 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 506 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 507 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 508 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 509 510 /* enable the ID buf for read */ 511 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 512 #define IWM_WFMP_MAC_ADDR_0 0xa03080 513 #define IWM_WFMP_MAC_ADDR_1 0xa03084 514 #define IWM_LMPM_PMG_EN 0xa01cec 515 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 516 #define IWM_RFIC_REG_RD 0xad0470 517 #define IWM_WFPM_CTRL_REG 0xa03030 518 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 519 #define IWM_ENABLE_WFPM 0x80000000 520 521 #define IWM_AUX_MISC_REG 0xa200b0 522 #define IWM_HW_STEP_LOCATION_BITS 24 523 524 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 525 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 526 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 527 #define IWM_RSA_ENABLE 0xa24b08 528 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 529 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 530 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 531 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 532 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 533 #define IWM_SB_CPU_1_STATUS 0xa01e30 534 #define IWM_SB_CPU_2_STATUS 0Xa01e34 535 536 /* Used to enable DBGM */ 537 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 538 539 /* 540 * Per-Tx-queue write pointer (index, really!) 541 * Indicates index to next TFD that driver will fill (1 past latest filled). 542 * Bit usage: 543 * 0-7: queue write index 544 * 11-8: queue selector 545 */ 546 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 547 548 /********************************************************** 549 * CSR values 550 **********************************************************/ 551 /* 552 * host interrupt timeout value 553 * used with setting interrupt coalescing timer 554 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 555 * 556 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 557 */ 558 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 559 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 560 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 561 #define IWM_HOST_INT_OPER_MODE (1U << 31) 562 563 /***************************************************************************** 564 * 7000/3000 series SHR DTS addresses * 565 *****************************************************************************/ 566 567 /* Diode Results Register Structure: */ 568 enum iwm_dtd_diode_reg { 569 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 570 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 571 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 572 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 573 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 574 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 575 /* Those are the masks INSIDE the flags bit-field: */ 576 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 577 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 578 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 579 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 580 }; 581 582 /** 583 * enum iwm_ucode_tlv_flag - ucode API flags 584 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 585 * was a separate TLV but moved here to save space. 586 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 587 * treats good CRC threshold as a boolean 588 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 589 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 590 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 591 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 592 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 593 * offload profile config command. 594 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 595 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 596 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 597 * (rather than two) IPv6 addresses 598 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 599 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 600 * from the probe request template. 601 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 602 * connection when going back to D0 603 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 604 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 605 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 606 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 607 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 608 * containing CAM (Continuous Active Mode) indication. 609 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 610 * single bound interface). 611 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 612 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 613 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 614 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 615 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 616 * 617 */ 618 enum iwm_ucode_tlv_flag { 619 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 620 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 621 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 622 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 623 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 624 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 625 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 626 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 627 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 628 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 629 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 630 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 631 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 632 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 633 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 634 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 635 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 636 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 637 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 638 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 639 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 640 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 641 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 642 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 643 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 644 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 645 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 646 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1U << 31), 647 }; 648 #define IWM_UCODE_TLV_FLAG_BITS \ 649 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 650 651 /** 652 * enum iwm_ucode_tlv_api - ucode api 653 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 654 * longer than the passive one, which is essential for fragmented scan. 655 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 656 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 657 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 658 * @IWM_UCODE_TLV_API_NEW_VERSION: new versioning format 659 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 660 * (command version 3) that supports per-chain limits 661 * @IWM_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan 662 * iteration complete notification, and the timestamp reported for RX 663 * received during scan, are reported in TSF of the mac specified in the 664 * scan request. 665 * @IWM_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of 666 * ADD_MODIFY_STA_KEY_API_S_VER_2. 667 * @IWM_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignment. 668 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 669 * instead of 3. 670 * @IWM_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used 671 * 672 * @IWM_NUM_UCODE_TLV_API: number of bits used 673 */ 674 enum iwm_ucode_tlv_api { 675 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8, 676 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9, 677 IWM_UCODE_TLV_API_WIDE_CMD_HDR = 14, 678 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18, 679 IWM_UCODE_TLV_API_NEW_VERSION = 20, 680 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = 24, 681 IWM_UCODE_TLV_API_TX_POWER_CHAIN = 27, 682 IWM_UCODE_TLV_API_SCAN_TSF_REPORT = 28, 683 IWM_UCODE_TLV_API_TKIP_MIC_KEYS = 29, 684 IWM_UCODE_TLV_API_STA_TYPE = 30, 685 IWM_UCODE_TLV_API_NAN2_VER2 = 31, 686 IWM_UCODE_TLV_API_ADAPTIVE_DWELL = 32, 687 IWM_UCODE_TLV_API_NEW_RX_STATS = 35, 688 IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY = 38, 689 IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 = 42, 690 IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER = 58, 691 692 IWM_NUM_UCODE_TLV_API = 128 693 }; 694 695 #define IWM_UCODE_TLV_API_BITS \ 696 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS" 697 698 /** 699 * enum iwm_ucode_tlv_capa - ucode capabilities 700 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 701 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 702 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 703 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 704 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 705 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 706 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 707 * tx power value into TPC Report action frame and Link Measurement Report 708 * action frame 709 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 710 * channel in DS parameter set element in probe requests. 711 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 712 * probe requests. 713 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 714 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 715 * which also implies support for the scheduler configuration command 716 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 717 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 718 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 719 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 720 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 721 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 722 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 723 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 724 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 725 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 726 * sources for the MCC. This TLV bit is a future replacement to 727 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 728 * is supported. 729 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 730 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 731 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 732 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 733 * 0=no support) 734 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 735 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 736 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 737 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 738 * antenna the beacon should be transmitted 739 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 740 * from AP and will send it upon d0i3 exit. 741 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 742 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 743 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 744 * thresholds reporting 745 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 746 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 747 * regular image. 748 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 749 * memory addresses from the firmware. 750 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 751 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 752 * 0=no support) 753 * 754 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 755 */ 756 enum iwm_ucode_tlv_capa { 757 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 758 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 759 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 760 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 761 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 762 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 763 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 764 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 765 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 766 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 767 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 768 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 769 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 770 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 771 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 772 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 773 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 774 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 775 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 776 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 777 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 778 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 779 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 780 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 781 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 782 IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT = 37, 783 IWM_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT = 39, 784 IWM_UCODE_TLV_CAPA_CDB_SUPPORT = 40, 785 IWM_UCODE_TLV_CAPA_DYNAMIC_QUOTA = 44, 786 IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS = 48, 787 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 788 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 789 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 790 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 791 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 792 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 793 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V3 = 73, 794 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 795 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 796 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 797 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 798 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 799 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 800 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 801 802 IWM_NUM_UCODE_TLV_CAPA = 128 803 }; 804 805 /* The default calibrate table size if not specified by firmware file */ 806 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 807 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 808 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 809 810 /* The default max probe length if not specified by the firmware file */ 811 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 812 813 /* 814 * enumeration of ucode section. 815 * This enumeration is used directly for older firmware (before 16.0). 816 * For new firmware, there can be up to 4 sections (see below) but the 817 * first one packaged into the firmware file is the DATA section and 818 * some debugging code accesses that. 819 */ 820 enum iwm_ucode_sec { 821 IWM_UCODE_SECTION_DATA, 822 IWM_UCODE_SECTION_INST, 823 }; 824 /* 825 * For 16.0 uCode and above, there is no differentiation between sections, 826 * just an offset to the HW address. 827 */ 828 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 829 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 830 831 /* uCode version contains 4 values: Major/Minor/API/Serial */ 832 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 833 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 834 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 835 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 836 837 /* 838 * Calibration control struct. 839 * Sent as part of the phy configuration command. 840 * @flow_trigger: bitmap for which calibrations to perform according to 841 * flow triggers. 842 * @event_trigger: bitmap for which calibrations to perform according to 843 * event triggers. 844 */ 845 struct iwm_tlv_calib_ctrl { 846 uint32_t flow_trigger; 847 uint32_t event_trigger; 848 } __packed; 849 850 enum iwm_fw_phy_cfg { 851 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 852 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 853 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 854 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 855 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 856 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 857 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 858 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 859 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 860 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 861 }; 862 863 #define IWM_UCODE_MAX_CS 1 864 865 /** 866 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 867 * @cipher: a cipher suite selector 868 * @flags: cipher scheme flags (currently reserved for a future use) 869 * @hdr_len: a size of MPDU security header 870 * @pn_len: a size of PN 871 * @pn_off: an offset of pn from the beginning of the security header 872 * @key_idx_off: an offset of key index byte in the security header 873 * @key_idx_mask: a bit mask of key_idx bits 874 * @key_idx_shift: bit shift needed to get key_idx 875 * @mic_len: mic length in bytes 876 * @hw_cipher: a HW cipher index used in host commands 877 */ 878 struct iwm_fw_cipher_scheme { 879 uint32_t cipher; 880 uint8_t flags; 881 uint8_t hdr_len; 882 uint8_t pn_len; 883 uint8_t pn_off; 884 uint8_t key_idx_off; 885 uint8_t key_idx_mask; 886 uint8_t key_idx_shift; 887 uint8_t mic_len; 888 uint8_t hw_cipher; 889 } __packed; 890 891 /** 892 * struct iwm_fw_cscheme_list - a cipher scheme list 893 * @size: a number of entries 894 * @cs: cipher scheme entries 895 */ 896 struct iwm_fw_cscheme_list { 897 uint8_t size; 898 struct iwm_fw_cipher_scheme cs[]; 899 } __packed; 900 901 /* v1/v2 uCode file layout */ 902 struct iwm_ucode_header { 903 uint32_t ver; /* major/minor/API/serial */ 904 union { 905 struct { 906 uint32_t inst_size; /* bytes of runtime code */ 907 uint32_t data_size; /* bytes of runtime data */ 908 uint32_t init_size; /* bytes of init code */ 909 uint32_t init_data_size; /* bytes of init data */ 910 uint32_t boot_size; /* bytes of bootstrap code */ 911 uint8_t data[0]; /* in same order as sizes */ 912 } v1; 913 struct { 914 uint32_t build; /* build number */ 915 uint32_t inst_size; /* bytes of runtime code */ 916 uint32_t data_size; /* bytes of runtime data */ 917 uint32_t init_size; /* bytes of init code */ 918 uint32_t init_data_size; /* bytes of init data */ 919 uint32_t boot_size; /* bytes of bootstrap code */ 920 uint8_t data[0]; /* in same order as sizes */ 921 } v2; 922 } u; 923 }; 924 925 /* 926 * new TLV uCode file layout 927 * 928 * The new TLV file format contains TLVs, that each specify 929 * some piece of data. 930 */ 931 932 enum iwm_ucode_tlv_type { 933 IWM_UCODE_TLV_INVALID = 0, /* unused */ 934 IWM_UCODE_TLV_INST = 1, 935 IWM_UCODE_TLV_DATA = 2, 936 IWM_UCODE_TLV_INIT = 3, 937 IWM_UCODE_TLV_INIT_DATA = 4, 938 IWM_UCODE_TLV_BOOT = 5, 939 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 940 IWM_UCODE_TLV_PAN = 7, 941 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 942 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 943 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 944 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 945 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 946 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 947 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 948 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 949 IWM_UCODE_TLV_WOWLAN_INST = 16, 950 IWM_UCODE_TLV_WOWLAN_DATA = 17, 951 IWM_UCODE_TLV_FLAGS = 18, 952 IWM_UCODE_TLV_SEC_RT = 19, 953 IWM_UCODE_TLV_SEC_INIT = 20, 954 IWM_UCODE_TLV_SEC_WOWLAN = 21, 955 IWM_UCODE_TLV_DEF_CALIB = 22, 956 IWM_UCODE_TLV_PHY_SKU = 23, 957 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 958 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 959 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 960 IWM_UCODE_TLV_NUM_OF_CPU = 27, 961 IWM_UCODE_TLV_CSCHEME = 28, 962 963 /* 964 * Following two are not in our base tag, but allow 965 * handling ucode version 9. 966 */ 967 IWM_UCODE_TLV_API_CHANGES_SET = 29, 968 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 969 970 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 971 IWM_UCODE_TLV_PAGING = 32, 972 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 973 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 974 IWM_UCODE_TLV_FW_VERSION = 36, 975 IWM_UCODE_TLV_FW_DBG_DEST = 38, 976 IWM_UCODE_TLV_FW_DBG_CONF = 39, 977 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 978 IWM_UCODE_TLV_CMD_VERSIONS = 48, 979 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 980 IWM_UCODE_TLV_FW_MEM_SEG = 51, 981 IWM_UCODE_TLV_UMAC_DEBUG_ADDRS = 54, 982 IWM_UCODE_TLV_LMAC_DEBUG_ADDRS = 55, 983 IWM_UCODE_TLV_HW_TYPE = 58 984 }; 985 986 struct iwm_ucode_tlv { 987 uint32_t type; /* see above */ 988 uint32_t length; /* not including type/length fields */ 989 uint8_t data[0]; 990 }; 991 992 struct iwm_ucode_api { 993 uint32_t api_index; 994 uint32_t api_flags; 995 } __packed; 996 997 struct iwm_ucode_capa { 998 uint32_t api_index; 999 uint32_t api_capa; 1000 } __packed; 1001 1002 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 1003 1004 struct iwm_tlv_ucode_header { 1005 /* 1006 * The TLV style ucode header is distinguished from 1007 * the v1/v2 style header by first four bytes being 1008 * zero, as such is an invalid combination of 1009 * major/minor/API/serial versions. 1010 */ 1011 uint32_t zero; 1012 uint32_t magic; 1013 uint8_t human_readable[64]; 1014 uint32_t ver; /* major/minor/API/serial */ 1015 uint32_t build; 1016 uint64_t ignore; 1017 /* 1018 * The data contained herein has a TLV layout, 1019 * see above for the TLV header and types. 1020 * Note that each TLV is padded to a length 1021 * that is a multiple of 4 for alignment. 1022 */ 1023 uint8_t data[0]; 1024 }; 1025 1026 /* 1027 * Registers in this file are internal, not PCI bus memory mapped. 1028 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1029 */ 1030 #define IWM_PRPH_BASE (0x00000) 1031 #define IWM_PRPH_END (0xFFFFF) 1032 1033 /* APMG (power management) constants */ 1034 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1035 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1036 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1037 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1038 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1039 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1040 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1041 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1042 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1043 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1044 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1045 1046 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1047 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1048 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1049 1050 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1051 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1052 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1053 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1054 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1055 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1056 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1057 1058 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1059 1060 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1061 1062 /* Device system time */ 1063 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1064 1065 /* Device NMI register */ 1066 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1067 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1068 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1069 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1070 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1071 1072 /* 1073 * Device reset for family 8000 1074 * write to bit 24 in order to reset the CPU 1075 */ 1076 #define IWM_RELEASE_CPU_RESET 0x300c 1077 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1078 1079 1080 /***************************************************************************** 1081 * 7000/3000 series SHR DTS addresses * 1082 *****************************************************************************/ 1083 1084 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1085 #define IWM_DTSC_CFG_MODE (0x00a10604) 1086 #define IWM_DTSC_VREF_AVG (0x00a10648) 1087 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1088 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1089 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1090 1091 1092 /** 1093 * Tx Scheduler 1094 * 1095 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1096 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1097 * host DRAM. It steers each frame's Tx command (which contains the frame 1098 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1099 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1100 * but one DMA channel may take input from several queues. 1101 * 1102 * Tx DMA FIFOs have dedicated purposes. 1103 * 1104 * For 5000 series and up, they are used differently 1105 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1106 * 1107 * 0 -- EDCA BK (background) frames, lowest priority 1108 * 1 -- EDCA BE (best effort) frames, normal priority 1109 * 2 -- EDCA VI (video) frames, higher priority 1110 * 3 -- EDCA VO (voice) and management frames, highest priority 1111 * 4 -- unused 1112 * 5 -- unused 1113 * 6 -- unused 1114 * 7 -- Commands 1115 * 1116 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1117 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1118 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1119 * 1120 * The driver sets up each queue to work in one of two modes: 1121 * 1122 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1123 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1124 * contains TFDs for a unique combination of Recipient Address (RA) 1125 * and Traffic Identifier (TID), that is, traffic of a given 1126 * Quality-Of-Service (QOS) priority, destined for a single station. 1127 * 1128 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1129 * each frame within the BA window, including whether it's been transmitted, 1130 * and whether it's been acknowledged by the receiving station. The device 1131 * automatically processes block-acks received from the receiving STA, 1132 * and reschedules un-acked frames to be retransmitted (successful 1133 * Tx completion may end up being out-of-order). 1134 * 1135 * The driver must maintain the queue's Byte Count table in host DRAM 1136 * for this mode. 1137 * This mode does not support fragmentation. 1138 * 1139 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1140 * The device may automatically retry Tx, but will retry only one frame 1141 * at a time, until receiving ACK from receiving station, or reaching 1142 * retry limit and giving up. 1143 * 1144 * The command queue (#4/#9) must use this mode! 1145 * This mode does not require use of the Byte Count table in host DRAM. 1146 * 1147 * Driver controls scheduler operation via 3 means: 1148 * 1) Scheduler registers 1149 * 2) Shared scheduler data base in internal SRAM 1150 * 3) Shared data in host DRAM 1151 * 1152 * Initialization: 1153 * 1154 * When loading, driver should allocate memory for: 1155 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1156 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1157 * (1024 bytes for each queue). 1158 * 1159 * After receiving "Alive" response from uCode, driver must initialize 1160 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1161 * the driver can't issue commands!): 1162 */ 1163 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1164 1165 /** 1166 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1167 * can keep track of at one time when creating block-ack chains of frames. 1168 * Note that "64" matches the number of ack bits in a block-ack packet. 1169 */ 1170 #define IWM_SCD_WIN_SIZE 64 1171 #define IWM_SCD_FRAME_LIMIT 64 1172 1173 #define IWM_SCD_TXFIFO_POS_TID (0) 1174 #define IWM_SCD_TXFIFO_POS_RA (4) 1175 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1176 1177 /* agn SCD */ 1178 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1179 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1180 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1181 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1182 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1183 1184 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1185 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1186 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1187 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1188 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1189 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1190 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1191 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1192 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1193 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1194 1195 /* Context Data */ 1196 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1197 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1198 1199 /* Tx status */ 1200 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1201 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1202 1203 /* Translation Data */ 1204 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1205 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1206 1207 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1208 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1209 1210 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1211 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1212 1213 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1214 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1215 1216 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1217 1218 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1219 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1220 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1221 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1222 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1223 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1224 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1225 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1226 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1227 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1228 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1229 1230 static __inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1231 { 1232 if (chnl < 20) 1233 return IWM_SCD_BASE + 0x18 + chnl * 4; 1234 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1235 } 1236 1237 static __inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1238 { 1239 if (chnl < 20) 1240 return IWM_SCD_BASE + 0x68 + chnl * 4; 1241 return IWM_SCD_BASE + 0x2B4 + chnl * 4; 1242 } 1243 1244 static __inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1245 { 1246 if (chnl < 20) 1247 return IWM_SCD_BASE + 0x10c + chnl * 4; 1248 return IWM_SCD_BASE + 0x334 + chnl * 4; 1249 } 1250 1251 /*********************** END TX SCHEDULER *************************************/ 1252 1253 /* Oscillator clock */ 1254 #define IWM_OSC_CLK (0xa04068) 1255 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1256 1257 /****************************/ 1258 /* Flow Handler Definitions */ 1259 /****************************/ 1260 1261 /** 1262 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1263 * Addresses are offsets from device's PCI hardware base address. 1264 */ 1265 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1266 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1267 1268 /** 1269 * Keep-Warm (KW) buffer base address. 1270 * 1271 * Driver must allocate a 4KByte buffer that is for keeping the 1272 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1273 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1274 * from going into a power-savings mode that would cause higher DRAM latency, 1275 * and possible data over/under-runs, before all Tx/Rx is complete. 1276 * 1277 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1278 * of the buffer, which must be 4K aligned. Once this is set up, the device 1279 * automatically invokes keep-warm accesses when normal accesses might not 1280 * be sufficient to maintain fast DRAM response. 1281 * 1282 * Bit fields: 1283 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1284 */ 1285 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1286 1287 1288 /** 1289 * TFD Circular Buffers Base (CBBC) addresses 1290 * 1291 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1292 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1293 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1294 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1295 * aligned (address bits 0-7 must be 0). 1296 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1297 * for them are in different places. 1298 * 1299 * Bit fields in each pointer register: 1300 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1301 */ 1302 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1303 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1304 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1305 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1306 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1307 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1308 1309 /* Find TFD CB base pointer for given queue */ 1310 static __inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1311 { 1312 if (chnl < 16) 1313 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1314 if (chnl < 20) 1315 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1316 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1317 } 1318 1319 1320 /** 1321 * Rx SRAM Control and Status Registers (RSCSR) 1322 * 1323 * These registers provide handshake between driver and device for the Rx queue 1324 * (this queue handles *all* command responses, notifications, Rx data, etc. 1325 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1326 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1327 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1328 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1329 * mapping between RBDs and RBs. 1330 * 1331 * Driver must allocate host DRAM memory for the following, and set the 1332 * physical address of each into device registers: 1333 * 1334 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1335 * entries (although any power of 2, up to 4096, is selectable by driver). 1336 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1337 * (typically 4K, although 8K or 16K are also selectable by driver). 1338 * Driver sets up RB size and number of RBDs in the CB via Rx config 1339 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1340 * 1341 * Bit fields within one RBD: 1342 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1343 * 1344 * Driver sets physical address [35:8] of base of RBD circular buffer 1345 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1346 * 1347 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1348 * (RBs) have been filled, via a "write pointer", actually the index of 1349 * the RB's corresponding RBD within the circular buffer. Driver sets 1350 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1351 * 1352 * Bit fields in lower dword of Rx status buffer (upper dword not used 1353 * by driver: 1354 * 31-12: Not used by driver 1355 * 11- 0: Index of last filled Rx buffer descriptor 1356 * (device writes, driver reads this value) 1357 * 1358 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1359 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1360 * and update the device's "write" index register, 1361 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1362 * 1363 * This "write" index corresponds to the *next* RBD that the driver will make 1364 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1365 * the circular buffer. This value should initially be 0 (before preparing any 1366 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1367 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1368 * "read" index has advanced past 1! See below). 1369 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1370 * 1371 * As the device fills RBs (referenced from contiguous RBDs within the circular 1372 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1373 * to tell the driver the index of the latest filled RBD. The driver must 1374 * read this "read" index from DRAM after receiving an Rx interrupt from device 1375 * 1376 * The driver must also internally keep track of a third index, which is the 1377 * next RBD to process. When receiving an Rx interrupt, driver should process 1378 * all filled but unprocessed RBs up to, but not including, the RB 1379 * corresponding to the "read" index. For example, if "read" index becomes "1", 1380 * driver may process the RB pointed to by RBD 0. Depending on volume of 1381 * traffic, there may be many RBs to process. 1382 * 1383 * If read index == write index, device thinks there is no room to put new data. 1384 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1385 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1386 * and "read" indexes; that is, make sure that there are no more than 254 1387 * buffers waiting to be filled. 1388 */ 1389 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1390 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1391 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1392 1393 /** 1394 * Physical base address of 8-byte Rx Status buffer. 1395 * Bit fields: 1396 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1397 */ 1398 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1399 1400 /** 1401 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1402 * Bit fields: 1403 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1404 */ 1405 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1406 1407 /** 1408 * Rx write pointer (index, really!). 1409 * Bit fields: 1410 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1411 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1412 */ 1413 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1414 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1415 1416 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1417 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1418 1419 /** 1420 * Rx Config/Status Registers (RCSR) 1421 * Rx Config Reg for channel 0 (only channel used) 1422 * 1423 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1424 * normal operation (see bit fields). 1425 * 1426 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1427 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1428 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1429 * 1430 * Bit fields: 1431 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1432 * '10' operate normally 1433 * 29-24: reserved 1434 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1435 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1436 * 19-18: reserved 1437 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1438 * '10' 12K, '11' 16K. 1439 * 15-14: reserved 1440 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1441 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1442 * typical value 0x10 (about 1/2 msec) 1443 * 3- 0: reserved 1444 */ 1445 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1446 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1447 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1448 1449 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1450 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1451 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1452 1453 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1454 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1455 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1456 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1457 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1458 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1459 1460 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1461 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1462 #define IWM_RX_RB_TIMEOUT (0x11) 1463 1464 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1465 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1466 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1467 1468 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1469 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1470 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1471 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1472 1473 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1474 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1475 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1476 1477 /** 1478 * Rx Shared Status Registers (RSSR) 1479 * 1480 * After stopping Rx DMA channel (writing 0 to 1481 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1482 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1483 * 1484 * Bit fields: 1485 * 24: 1 = Channel 0 is idle 1486 * 1487 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1488 * contain default values that should not be altered by the driver. 1489 */ 1490 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1491 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1492 1493 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1494 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1495 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1496 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1497 1498 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1499 1500 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1501 1502 /* TFDB Area - TFDs buffer table */ 1503 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1504 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1505 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1506 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1507 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1508 1509 /** 1510 * Transmit DMA Channel Control/Status Registers (TCSR) 1511 * 1512 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1513 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1514 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1515 * 1516 * To use a Tx DMA channel, driver must initialize its 1517 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1518 * 1519 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1520 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1521 * 1522 * All other bits should be 0. 1523 * 1524 * Bit fields: 1525 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1526 * '10' operate normally 1527 * 29- 4: Reserved, set to "0" 1528 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1529 * 2- 0: Reserved, set to "0" 1530 */ 1531 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1532 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1533 1534 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1535 #define IWM_FH_TCSR_CHNL_NUM (8) 1536 1537 /* TCSR: tx_config register values */ 1538 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1539 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1540 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1541 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1542 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1543 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1544 1545 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1546 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1547 1548 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1549 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1550 1551 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1552 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1553 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1554 1555 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1556 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1557 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1558 1559 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1560 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1561 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1562 1563 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1564 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1565 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1566 1567 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1568 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1569 1570 /** 1571 * Tx Shared Status Registers (TSSR) 1572 * 1573 * After stopping Tx DMA channel (writing 0 to 1574 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1575 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1576 * (channel's buffers empty | no pending requests). 1577 * 1578 * Bit fields: 1579 * 31-24: 1 = Channel buffers empty (channel 7:0) 1580 * 23-16: 1 = No pending requests (channel 7:0) 1581 */ 1582 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1583 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1584 1585 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1586 1587 /** 1588 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1589 * 31: Indicates an address error when accessed to internal memory 1590 * uCode/driver must write "1" in order to clear this flag 1591 * 30: Indicates that Host did not send the expected number of dwords to FH 1592 * uCode/driver must write "1" in order to clear this flag 1593 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1594 * command was received from the scheduler while the TRB was already full 1595 * with previous command 1596 * uCode/driver must write "1" in order to clear this flag 1597 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1598 * bit is set, it indicates that the FH has received a full indication 1599 * from the RTC TxFIFO and the current value of the TxCredit counter was 1600 * not equal to zero. This mean that the credit mechanism was not 1601 * synchronized to the TxFIFO status 1602 * uCode/driver must write "1" in order to clear this flag 1603 */ 1604 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1605 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1606 1607 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1608 1609 /* Tx service channels */ 1610 #define IWM_FH_SRVC_CHNL (9) 1611 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1612 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1613 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1614 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1615 1616 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1617 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1618 (_chan) * 4) 1619 1620 /* Instruct FH to increment the retry count of a packet when 1621 * it is brought from the memory to TX-FIFO 1622 */ 1623 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1624 1625 #define IWM_RX_QUEUE_SIZE 256 1626 #define IWM_RX_QUEUE_MASK 255 1627 #define IWM_RX_QUEUE_SIZE_LOG 8 1628 1629 /* 1630 * RX related structures and functions 1631 */ 1632 #define IWM_RX_FREE_BUFFERS 64 1633 #define IWM_RX_LOW_WATERMARK 8 1634 1635 /** 1636 * struct iwm_rb_status - reseve buffer status 1637 * host memory mapped FH registers 1638 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1639 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1640 * @finished_rb_num [0:11] - Indicates the index of the current RB 1641 * in which the last frame was written to 1642 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1643 * which was transferred 1644 */ 1645 struct iwm_rb_status { 1646 uint16_t closed_rb_num; 1647 uint16_t closed_fr_num; 1648 uint16_t finished_rb_num; 1649 uint16_t finished_fr_nam; 1650 uint32_t unused; 1651 } __packed; 1652 1653 1654 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1655 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1656 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1657 IWM_TFD_QUEUE_SIZE_BC_DUP) 1658 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1659 #define IWM_NUM_OF_TBS 20 1660 1661 static __inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1662 { 1663 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1664 } 1665 /** 1666 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1667 * 1668 * This structure contains dma address and length of transmission address 1669 * 1670 * @lo: low [31:0] portion of the dma address of TX buffer 1671 * every even is unaligned on 16 bit boundary 1672 * @hi_n_len 0-3 [35:32] portion of dma 1673 * 4-15 length of the tx buffer 1674 */ 1675 struct iwm_tfd_tb { 1676 uint32_t lo; 1677 uint16_t hi_n_len; 1678 } __packed; 1679 1680 /** 1681 * struct iwm_tfd 1682 * 1683 * Transmit Frame Descriptor (TFD) 1684 * 1685 * @ __reserved1[3] reserved 1686 * @ num_tbs 0-4 number of active tbs 1687 * 5 reserved 1688 * 6-7 padding (not used) 1689 * @ tbs[20] transmit frame buffer descriptors 1690 * @ __pad padding 1691 * 1692 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1693 * Both driver and device share these circular buffers, each of which must be 1694 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1695 * 1696 * Driver must indicate the physical address of the base of each 1697 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1698 * 1699 * Each TFD contains pointer/size information for up to 20 data buffers 1700 * in host DRAM. These buffers collectively contain the (one) frame described 1701 * by the TFD. Each buffer must be a single contiguous block of memory within 1702 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1703 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1704 * Tx frame, up to 8 KBytes in size. 1705 * 1706 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1707 */ 1708 struct iwm_tfd { 1709 uint8_t __reserved1[3]; 1710 uint8_t num_tbs; 1711 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1712 uint32_t __pad; 1713 } __packed; 1714 1715 /* Keep Warm Size */ 1716 #define IWM_KW_SIZE 0x1000 /* 4k */ 1717 1718 /* Fixed (non-configurable) rx data from phy */ 1719 1720 /** 1721 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1722 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1723 * @tfd_offset 0-12 - tx command byte count 1724 * 12-16 - station index 1725 */ 1726 struct iwm_agn_scd_bc_tbl { 1727 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1728 } __packed; 1729 1730 #define IWM_TX_CRC_SIZE 4 1731 #define IWM_TX_DELIMITER_SIZE 4 1732 1733 /* Maximum number of Tx queues. */ 1734 #define IWM_MAX_QUEUES 31 1735 1736 /** 1737 * DQA - Dynamic Queue Allocation -introduction 1738 * 1739 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi 1740 * to allow dynamic allocation of queues on-demand, rather than allocate them 1741 * statically ahead of time. Ideally, we would like to allocate one queue 1742 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2 1743 * even if it also needs to send traffic to a sleeping STA1, without being 1744 * blocked by the sleeping station. 1745 * 1746 * Although the queues in DQA mode are dynamically allocated, there are still 1747 * some queues that are statically allocated: 1748 * TXQ #0 - command queue 1749 * TXQ #1 - aux frames 1750 * TXQ #2 - P2P device frames 1751 * TXQ #3 - P2P GO/SoftAP GCAST/BCAST frames 1752 * TXQ #4 - BSS DATA frames queue 1753 * TXQ #5-8 - non-QoS data, QoS no-data, and MGMT frames queue pool 1754 * TXQ #9 - P2P GO/SoftAP probe responses 1755 * TXQ #10-31 - QoS DATA frames queue pool (for Tx aggregation) 1756 */ 1757 1758 /* static DQA Tx queue numbers */ 1759 enum { 1760 IWM_DQA_CMD_QUEUE = 0, 1761 IWM_DQA_AUX_QUEUE = 1, 1762 IWM_DQA_P2P_DEVICE_QUEUE = 2, 1763 IWM_DQA_INJECT_MONITOR_QUEUE = 2 , 1764 IWM_DQA_GCAST_QUEUE = 3, 1765 IWM_DQA_BSS_CLIENT_QUEUE = 4, 1766 IWM_DQA_MIN_MGMT_QUEUE = 5, 1767 IWM_DQA_MAX_MGMT_QUEUE = 8, 1768 IWM_DQA_AP_PROBE_RESP_QUEUE = 9, 1769 IWM_DQA_MIN_DATA_QUEUE = 10, 1770 IWM_DQA_MAX_DATA_QUEUE = 31, 1771 }; 1772 1773 /* Reserve 8 DQA Tx queues, from 10 up to 17, for A-MPDU aggregation. */ 1774 #define IWM_FIRST_AGG_TX_QUEUE IWM_DQA_MIN_DATA_QUEUE 1775 #define IWM_LAST_AGG_TX_QUEUE (IWM_FIRST_AGG_TX_QUEUE + IWM_MAX_TID_COUNT - 1) 1776 1777 /* legacy non-DQA queues; the legacy command queue uses a different number! */ 1778 enum { 1779 IWM_OFFCHANNEL_QUEUE = 8, 1780 IWM_CMD_QUEUE = 9, 1781 IWM_AUX_QUEUE = 15, 1782 }; 1783 1784 enum iwm_mvm_tx_fifo { 1785 IWM_TX_FIFO_BK = 0, 1786 IWM_TX_FIFO_BE, 1787 IWM_TX_FIFO_VI, 1788 IWM_TX_FIFO_VO, 1789 IWM_TX_FIFO_MCAST = 5, 1790 IWM_TX_FIFO_CMD = 7, 1791 }; 1792 1793 #define IWM_STATION_COUNT 16 1794 1795 /* commands */ 1796 enum { 1797 IWM_ALIVE = 0x1, 1798 IWM_REPLY_ERROR = 0x2, 1799 1800 IWM_INIT_COMPLETE_NOTIF = 0x4, 1801 1802 /* PHY context commands */ 1803 IWM_PHY_CONTEXT_CMD = 0x8, 1804 IWM_DBG_CFG = 0x9, 1805 1806 /* UMAC scan commands */ 1807 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1808 IWM_SCAN_CFG_CMD = 0xc, 1809 IWM_SCAN_REQ_UMAC = 0xd, 1810 IWM_SCAN_ABORT_UMAC = 0xe, 1811 IWM_SCAN_COMPLETE_UMAC = 0xf, 1812 1813 /* station table */ 1814 IWM_ADD_STA_KEY = 0x17, 1815 IWM_ADD_STA = 0x18, 1816 IWM_REMOVE_STA = 0x19, 1817 1818 /* TX */ 1819 IWM_TX_CMD = 0x1c, 1820 IWM_TXPATH_FLUSH = 0x1e, 1821 IWM_MGMT_MCAST_KEY = 0x1f, 1822 1823 /* scheduler config */ 1824 IWM_SCD_QUEUE_CFG = 0x1d, 1825 1826 /* global key */ 1827 IWM_WEP_KEY = 0x20, 1828 1829 /* MAC and Binding commands */ 1830 IWM_MAC_CONTEXT_CMD = 0x28, 1831 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1832 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1833 IWM_BINDING_CONTEXT_CMD = 0x2b, 1834 IWM_TIME_QUOTA_CMD = 0x2c, 1835 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1836 1837 IWM_LQ_CMD = 0x4e, 1838 1839 /* Calibration */ 1840 IWM_TEMPERATURE_NOTIFICATION = 0x62, 1841 IWM_CALIBRATION_CFG_CMD = 0x65, 1842 IWM_CALIBRATION_RES_NOTIFICATION = 0x66, 1843 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67, 1844 IWM_RADIO_VERSION_NOTIFICATION = 0x68, 1845 1846 /* paging block to FW cpu2 */ 1847 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1848 1849 /* Scan offload */ 1850 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1851 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1852 IWM_HOT_SPOT_CMD = 0x53, 1853 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1854 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1855 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1856 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1857 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1858 1859 /* Phy */ 1860 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1861 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1862 IWM_PHY_DB_CMD = 0x6c, 1863 1864 /* Power - legacy power table command */ 1865 IWM_POWER_TABLE_CMD = 0x77, 1866 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1867 IWM_LTR_CONFIG = 0xee, 1868 1869 /* Thermal Throttling*/ 1870 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1871 1872 /* Scanning */ 1873 IWM_SCAN_REQUEST_CMD = 0x80, 1874 IWM_SCAN_ABORT_CMD = 0x81, 1875 IWM_SCAN_START_NOTIFICATION = 0x82, 1876 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1877 IWM_SCAN_COMPLETE_NOTIFICATION = 0x84, 1878 1879 /* NVM */ 1880 IWM_NVM_ACCESS_CMD = 0x88, 1881 1882 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1883 1884 IWM_BEACON_NOTIFICATION = 0x90, 1885 IWM_BEACON_TEMPLATE_CMD = 0x91, 1886 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1887 IWM_BT_CONFIG = 0x9b, 1888 IWM_STATISTICS_NOTIFICATION = 0x9d, 1889 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1890 1891 /* RF-KILL commands and notifications */ 1892 IWM_CARD_STATE_CMD = 0xa0, 1893 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1894 1895 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1896 1897 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1898 1899 /* Power - new power table command */ 1900 IWM_MAC_PM_POWER_TABLE = 0xa9, 1901 1902 IWM_REPLY_RX_PHY_CMD = 0xc0, 1903 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1904 IWM_BA_NOTIF = 0xc5, 1905 1906 /* Location Aware Regulatory */ 1907 IWM_MCC_UPDATE_CMD = 0xc8, 1908 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1909 1910 /* BT Coex */ 1911 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1912 IWM_BT_COEX_PROT_ENV = 0xcd, 1913 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1914 IWM_BT_COEX_CI = 0x5d, 1915 1916 IWM_REPLY_SF_CFG_CMD = 0xd1, 1917 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1918 1919 /* DTS measurements */ 1920 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1921 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1922 1923 IWM_REPLY_DEBUG_CMD = 0xf0, 1924 IWM_DEBUG_LOG_MSG = 0xf7, 1925 1926 IWM_MCAST_FILTER_CMD = 0xd0, 1927 1928 /* D3 commands/notifications */ 1929 IWM_D3_CONFIG_CMD = 0xd3, 1930 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1931 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1932 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1933 1934 /* for WoWLAN in particular */ 1935 IWM_WOWLAN_PATTERNS = 0xe0, 1936 IWM_WOWLAN_CONFIGURATION = 0xe1, 1937 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1938 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1939 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1940 IWM_WOWLAN_GET_STATUSES = 0xe5, 1941 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1942 1943 /* and for NetDetect */ 1944 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1945 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1946 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1947 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1948 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1949 1950 /* system group command IDs */ 1951 IWM_FSEQ_VER_MISMATCH_NOTIFICATION = 0xff, 1952 1953 IWM_REPLY_MAX = 0xff, 1954 }; 1955 1956 enum iwm_phy_ops_subcmd_ids { 1957 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1958 IWM_CTDP_CONFIG_CMD = 0x03, 1959 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1960 IWM_CT_KILL_NOTIFICATION = 0xFE, 1961 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1962 }; 1963 1964 /* command groups */ 1965 enum { 1966 IWM_LEGACY_GROUP = 0x0, 1967 IWM_LONG_GROUP = 0x1, 1968 IWM_SYSTEM_GROUP = 0x2, 1969 IWM_MAC_CONF_GROUP = 0x3, 1970 IWM_PHY_OPS_GROUP = 0x4, 1971 IWM_DATA_PATH_GROUP = 0x5, 1972 IWM_PROT_OFFLOAD_GROUP = 0xb, 1973 }; 1974 1975 /* SYSTEM_GROUP group subcommand IDs */ 1976 enum { 1977 IWM_SHARED_MEM_CFG_CMD = 0x00, 1978 IWM_SOC_CONFIGURATION_CMD = 0x01, 1979 IWM_INIT_EXTENDED_CFG_CMD = 0x03, 1980 IWM_FW_ERROR_RECOVERY_CMD = 0x07, 1981 }; 1982 1983 /* DATA_PATH group subcommand IDs */ 1984 enum { 1985 IWM_DQA_ENABLE_CMD = 0x00, 1986 }; 1987 1988 1989 /* 1990 * struct iwm_dqa_enable_cmd 1991 * @cmd_queue: the TXQ number of the command queue 1992 */ 1993 struct iwm_dqa_enable_cmd { 1994 uint32_t cmd_queue; 1995 } __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */ 1996 1997 1998 /** 1999 * struct iwm_cmd_response - generic response struct for most commands 2000 * @status: status of the command asked, changes for each one 2001 */ 2002 struct iwm_cmd_response { 2003 uint32_t status; 2004 }; 2005 2006 /* 2007 * struct iwm_tx_ant_cfg_cmd 2008 * @valid: valid antenna configuration 2009 */ 2010 struct iwm_tx_ant_cfg_cmd { 2011 uint32_t valid; 2012 } __packed; 2013 2014 /** 2015 * struct iwm_reduce_tx_power_cmd - TX power reduction command 2016 * IWM_REDUCE_TX_POWER_CMD = 0x9f 2017 * @flags: (reserved for future implementation) 2018 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 2019 * @pwr_restriction: TX power restriction in dBms. 2020 */ 2021 struct iwm_reduce_tx_power_cmd { 2022 uint8_t flags; 2023 uint8_t mac_context_id; 2024 uint16_t pwr_restriction; 2025 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 2026 2027 /* 2028 * Calibration control struct. 2029 * Sent as part of the phy configuration command. 2030 * @flow_trigger: bitmap for which calibrations to perform according to 2031 * flow triggers. 2032 * @event_trigger: bitmap for which calibrations to perform according to 2033 * event triggers. 2034 */ 2035 struct iwm_calib_ctrl { 2036 uint32_t flow_trigger; 2037 uint32_t event_trigger; 2038 } __packed; 2039 2040 /* This enum defines the bitmap of various calibrations to enable in both 2041 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 2042 */ 2043 enum iwm_calib_cfg { 2044 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 2045 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 2046 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 2047 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 2048 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 2049 IWM_CALIB_CFG_DC_IDX = (1 << 5), 2050 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 2051 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 2052 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 2053 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 2054 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 2055 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 2056 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 2057 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 2058 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 2059 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 2060 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 2061 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 2062 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 2063 }; 2064 2065 /* 2066 * Phy configuration command. 2067 */ 2068 struct iwm_phy_cfg_cmd { 2069 uint32_t phy_cfg; 2070 struct iwm_calib_ctrl calib_control; 2071 } __packed; 2072 2073 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2074 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2075 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2076 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2077 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2078 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2079 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2080 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2081 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2082 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2083 2084 #define IWM_MAX_DTS_TRIPS 8 2085 2086 /** 2087 * struct iwm_ct_kill_notif - CT-kill entry notification 2088 * 2089 * @temperature: the current temperature in celsius 2090 * @reserved: reserved 2091 */ 2092 struct iwm_ct_kill_notif { 2093 uint16_t temperature; 2094 uint16_t reserved; 2095 } __packed; /* GRP_PHY_CT_KILL_NTF */ 2096 2097 /** 2098 * struct iwm_temp_report_ths_cmd - set temperature thresholds 2099 * (IWM_TEMP_REPORTING_THRESHOLDS_CMD) 2100 * 2101 * @num_temps: number of temperature thresholds passed 2102 * @thresholds: array with the thresholds to be configured 2103 */ 2104 struct iwm_temp_report_ths_cmd { 2105 uint32_t num_temps; 2106 uint16_t thresholds[IWM_MAX_DTS_TRIPS]; 2107 } __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */ 2108 2109 /* 2110 * PHY db 2111 */ 2112 2113 enum iwm_phy_db_section_type { 2114 IWM_PHY_DB_CFG = 1, 2115 IWM_PHY_DB_CALIB_NCH, 2116 IWM_PHY_DB_UNUSED, 2117 IWM_PHY_DB_CALIB_CHG_PAPD, 2118 IWM_PHY_DB_CALIB_CHG_TXP, 2119 IWM_PHY_DB_MAX 2120 }; 2121 2122 /* 2123 * phy db - configure operational ucode 2124 */ 2125 struct iwm_phy_db_cmd { 2126 uint16_t type; 2127 uint16_t length; 2128 uint8_t data[]; 2129 } __packed; 2130 2131 /* for parsing of tx power channel group data that comes from the firmware*/ 2132 struct iwm_phy_db_chg_txp { 2133 uint32_t space; 2134 uint16_t max_channel_idx; 2135 } __packed; 2136 2137 /* 2138 * phy db - Receive phy db chunk after calibrations 2139 */ 2140 struct iwm_calib_res_notif_phy_db { 2141 uint16_t type; 2142 uint16_t length; 2143 uint8_t data[]; 2144 } __packed; 2145 2146 /* 7k family NVM HW-Section offset (in words) definitions */ 2147 #define IWM_HW_ADDR 0x15 2148 /* 7k family NVM SW-Section offset (in words) definitions */ 2149 #define IWM_NVM_SW_SECTION 0x1C0 2150 #define IWM_NVM_VERSION 0 2151 #define IWM_RADIO_CFG 1 2152 #define IWM_SKU 2 2153 #define IWM_N_HW_ADDRS 3 2154 #define IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION 2155 /* 7k family NVM calibration section offset (in words) definitions */ 2156 #define IWM_NVM_CALIB_SECTION 0x2B8 2157 #define IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION) 2158 2159 /* 8k family NVM HW-Section offset (in words) definitions */ 2160 #define IWM_HW_ADDR0_WFPM_8000 0x12 2161 #define IWM_HW_ADDR1_WFPM_8000 0x16 2162 #define IWM_HW_ADDR0_PCIE_8000 0x8A 2163 #define IWM_HW_ADDR1_PCIE_8000 0x8E 2164 #define IWM_MAC_ADDRESS_OVERRIDE_8000 1 2165 2166 /* 8k family NVM SW-Section offset (in words) definitions */ 2167 #define IWM_NVM_SW_SECTION_8000 0x1C0 2168 #define IWM_NVM_VERSION_8000 0 2169 #define IWM_RADIO_CFG_8000 0 2170 #define IWM_SKU_8000 2 2171 #define IWM_N_HW_ADDRS_8000 3 2172 2173 /* 8k family NVM REGULATORY -Section offset (in words) definitions */ 2174 #define IWM_NVM_CHANNELS_8000 0 2175 #define IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7 2176 #define IWM_NVM_LAR_OFFSET_8000 0x507 2177 #define IWM_NVM_LAR_ENABLED_8000 0x7 2178 2179 /* 8k family NVM calibration section offset (in words) definitions */ 2180 #define IWM_NVM_CALIB_SECTION_8000 0x2B8 2181 #define IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000) 2182 2183 /* SKU Capabilities (actual values from NVM definition) */ 2184 #define IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0) 2185 #define IWM_NVM_SKU_CAP_BAND_52GHZ (1 << 1) 2186 #define IWM_NVM_SKU_CAP_11N_ENABLE (1 << 2) 2187 #define IWM_NVM_SKU_CAP_11AC_ENABLE (1 << 3) 2188 #define IWM_NVM_SKU_CAP_MIMO_DISABLE (1 << 5) 2189 2190 /* radio config bits (actual values from NVM definition) */ 2191 #define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */ 2192 #define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 2193 #define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 2194 #define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 2195 #define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 2196 #define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 2197 2198 #define IWM_NVM_RF_CFG_PNUM_MSK_8000(x) (x & 0xF) 2199 #define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF) 2200 #define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF) 2201 #define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF) 2202 #define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF) 2203 #define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF) 2204 2205 #define DEFAULT_MAX_TX_POWER 16 2206 2207 /* 2208 * channel flags in NVM 2209 * @IWM_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 2210 * @IWM_NVM_CHANNEL_IBSS: usable as an IBSS channel 2211 * @IWM_NVM_CHANNEL_ACTIVE: active scanning allowed 2212 * @IWM_NVM_CHANNEL_RADAR: radar detection required 2213 * @IWM_NVM_CHANNEL_DFS: dynamic freq selection candidate 2214 * @IWM_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 2215 * @IWM_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 2216 * @IWM_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 2217 * @IWM_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 2218 */ 2219 #define IWM_NVM_CHANNEL_VALID (1 << 0) 2220 #define IWM_NVM_CHANNEL_IBSS (1 << 1) 2221 #define IWM_NVM_CHANNEL_ACTIVE (1 << 3) 2222 #define IWM_NVM_CHANNEL_RADAR (1 << 4) 2223 #define IWM_NVM_CHANNEL_DFS (1 << 7) 2224 #define IWM_NVM_CHANNEL_WIDE (1 << 8) 2225 #define IWM_NVM_CHANNEL_40MHZ (1 << 9) 2226 #define IWM_NVM_CHANNEL_80MHZ (1 << 10) 2227 #define IWM_NVM_CHANNEL_160MHZ (1 << 11) 2228 2229 /* Target of the IWM_NVM_ACCESS_CMD */ 2230 enum { 2231 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2232 IWM_NVM_ACCESS_TARGET_OTP = 1, 2233 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2234 }; 2235 2236 /* Section types for IWM_NVM_ACCESS_CMD */ 2237 enum { 2238 IWM_NVM_SECTION_TYPE_HW = 0, 2239 IWM_NVM_SECTION_TYPE_SW, 2240 IWM_NVM_SECTION_TYPE_PAPD, 2241 IWM_NVM_SECTION_TYPE_REGULATORY, 2242 IWM_NVM_SECTION_TYPE_CALIBRATION, 2243 IWM_NVM_SECTION_TYPE_PRODUCTION, 2244 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB, 2245 /* 7 unknown */ 2246 IWM_NVM_SECTION_TYPE_REGULATORY_SDP = 8, 2247 /* 9 unknown */ 2248 IWM_NVM_SECTION_TYPE_HW_8000 = 10, 2249 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE, 2250 IWM_NVM_SECTION_TYPE_PHY_SKU, 2251 IWM_NVM_NUM_OF_SECTIONS, 2252 }; 2253 2254 /** 2255 * enum iwm_nvm_type - nvm formats 2256 * @IWM_NVM: the regular format 2257 * @IWM_NVM_EXT: extended NVM format 2258 * @IWM_NVM_SDP: NVM format used by 3168 series 2259 */ 2260 enum iwm_nvm_type { 2261 IWM_NVM, 2262 IWM_NVM_EXT, 2263 IWM_NVM_SDP, 2264 }; 2265 2266 /** 2267 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2268 * @op_code: 0 - read, 1 - write 2269 * @target: IWM_NVM_ACCESS_TARGET_* 2270 * @type: IWM_NVM_SECTION_TYPE_* 2271 * @offset: offset in bytes into the section 2272 * @length: in bytes, to read/write 2273 * @data: if write operation, the data to write. On read its empty 2274 */ 2275 struct iwm_nvm_access_cmd { 2276 uint8_t op_code; 2277 uint8_t target; 2278 uint16_t type; 2279 uint16_t offset; 2280 uint16_t length; 2281 uint8_t data[]; 2282 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2283 2284 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2285 2286 /* 2287 * struct iwm_fw_paging_cmd - paging layout 2288 * 2289 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2290 * 2291 * Send to FW the paging layout in the driver. 2292 * 2293 * @flags: various flags for the command 2294 * @block_size: the block size in powers of 2 2295 * @block_num: number of blocks specified in the command. 2296 * @device_phy_addr: virtual addresses from device side 2297 * 32 bit address for API version 1, 64 bit address for API version 2. 2298 */ 2299 struct iwm_fw_paging_cmd { 2300 uint32_t flags; 2301 uint32_t block_size; 2302 uint32_t block_num; 2303 union { 2304 uint32_t addr32[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2305 uint64_t addr64[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2306 } device_phy_addr; 2307 } __packed; /* FW_PAGING_BLOCK_CMD_API_S_VER_2 */ 2308 2309 /* 2310 * Fw items ID's 2311 * 2312 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2313 * download 2314 */ 2315 enum iwm_fw_item_id { 2316 IWM_FW_ITEM_ID_PAGING = 3, 2317 }; 2318 2319 /* 2320 * struct iwm_fw_get_item_cmd - get an item from the fw 2321 */ 2322 struct iwm_fw_get_item_cmd { 2323 uint32_t item_id; 2324 } __packed; /* FW_GET_ITEM_CMD_API_S_VER_1 */ 2325 2326 /** 2327 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2328 * @offset: offset in bytes into the section 2329 * @length: in bytes, either how much was written or read 2330 * @type: IWM_NVM_SECTION_TYPE_* 2331 * @status: 0 for success, fail otherwise 2332 * @data: if read operation, the data returned. Empty on write. 2333 */ 2334 struct iwm_nvm_access_resp { 2335 uint16_t offset; 2336 uint16_t length; 2337 uint16_t type; 2338 uint16_t status; 2339 uint8_t data[]; 2340 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2341 2342 /* IWM_ALIVE 0x1 */ 2343 2344 /* alive response is_valid values */ 2345 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2346 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2347 2348 /* alive response ver_type values */ 2349 enum { 2350 IWM_FW_TYPE_HW = 0, 2351 IWM_FW_TYPE_PROT = 1, 2352 IWM_FW_TYPE_AP = 2, 2353 IWM_FW_TYPE_WOWLAN = 3, 2354 IWM_FW_TYPE_TIMING = 4, 2355 IWM_FW_TYPE_WIPAN = 5 2356 }; 2357 2358 /* alive response ver_subtype values */ 2359 enum { 2360 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2361 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2362 IWM_FW_SUBTYPE_REDUCED = 2, 2363 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2364 IWM_FW_SUBTYPE_WOWLAN = 4, 2365 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2366 IWM_FW_SUBTYPE_WIPAN = 6, 2367 IWM_FW_SUBTYPE_INITIALIZE = 9 2368 }; 2369 2370 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2371 #define IWM_ALIVE_STATUS_OK 0xCAFE 2372 2373 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2374 2375 struct iwm_alive_resp_v1 { 2376 uint16_t status; 2377 uint16_t flags; 2378 uint8_t ucode_minor; 2379 uint8_t ucode_major; 2380 uint16_t id; 2381 uint8_t api_minor; 2382 uint8_t api_major; 2383 uint8_t ver_subtype; 2384 uint8_t ver_type; 2385 uint8_t mac; 2386 uint8_t opt; 2387 uint16_t reserved2; 2388 uint32_t timestamp; 2389 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2390 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2391 uint32_t cpu_register_ptr; 2392 uint32_t dbgm_config_ptr; 2393 uint32_t alive_counter_ptr; 2394 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2395 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2396 2397 struct iwm_alive_resp_v2 { 2398 uint16_t status; 2399 uint16_t flags; 2400 uint8_t ucode_minor; 2401 uint8_t ucode_major; 2402 uint16_t id; 2403 uint8_t api_minor; 2404 uint8_t api_major; 2405 uint8_t ver_subtype; 2406 uint8_t ver_type; 2407 uint8_t mac; 2408 uint8_t opt; 2409 uint16_t reserved2; 2410 uint32_t timestamp; 2411 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2412 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2413 uint32_t cpu_register_ptr; 2414 uint32_t dbgm_config_ptr; 2415 uint32_t alive_counter_ptr; 2416 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2417 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2418 uint32_t st_fwrd_size; 2419 uint8_t umac_minor; /* UMAC version: minor */ 2420 uint8_t umac_major; /* UMAC version: major */ 2421 uint16_t umac_id; /* UMAC version: id */ 2422 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2423 uint32_t dbg_print_buff_addr; 2424 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2425 2426 struct iwm_alive_resp_v3 { 2427 uint16_t status; 2428 uint16_t flags; 2429 uint32_t ucode_minor; 2430 uint32_t ucode_major; 2431 uint8_t ver_subtype; 2432 uint8_t ver_type; 2433 uint8_t mac; 2434 uint8_t opt; 2435 uint32_t timestamp; 2436 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2437 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2438 uint32_t cpu_register_ptr; 2439 uint32_t dbgm_config_ptr; 2440 uint32_t alive_counter_ptr; 2441 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2442 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2443 uint32_t st_fwrd_size; 2444 uint32_t umac_minor; /* UMAC version: minor */ 2445 uint32_t umac_major; /* UMAC version: major */ 2446 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2447 uint32_t dbg_print_buff_addr; 2448 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2449 2450 #define IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0) 2451 #define IWM_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1) 2452 2453 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc 2454 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0 2455 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_200 1 2456 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_2500 2 2457 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_1820 3 2458 2459 /** 2460 * struct iwm_soc_configuration_cmd - Set device stabilization latency 2461 * 2462 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE 2463 * flag, because the FW treats the whole value as an integer. In 2464 * VER_2, we can set the bits independently. 2465 * @latency: time for SOC to ensure stable power & XTAL 2466 */ 2467 struct iwm_soc_configuration_cmd { 2468 uint32_t flags; 2469 uint32_t latency; 2470 } __packed; /* 2471 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above) 2472 * SOC_CONFIGURATION_CMD_S_VER_2 2473 */ 2474 2475 2476 /* Error response/notification */ 2477 enum { 2478 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2479 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2480 IWM_FW_ERR_SERVICE = 0x2, 2481 IWM_FW_ERR_ARC_MEMORY = 0x3, 2482 IWM_FW_ERR_ARC_CODE = 0x4, 2483 IWM_FW_ERR_WATCH_DOG = 0x5, 2484 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2485 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2486 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2487 IWM_FW_ERR_UNEXPECTED = 0xFE, 2488 IWM_FW_ERR_FATAL = 0xFF 2489 }; 2490 2491 /** 2492 * struct iwm_error_resp - FW error indication 2493 * ( IWM_REPLY_ERROR = 0x2 ) 2494 * @error_type: one of IWM_FW_ERR_* 2495 * @cmd_id: the command ID for which the error occured 2496 * @bad_cmd_seq_num: sequence number of the erroneous command 2497 * @error_service: which service created the error, applicable only if 2498 * error_type = 2, otherwise 0 2499 * @timestamp: TSF in usecs. 2500 */ 2501 struct iwm_error_resp { 2502 uint32_t error_type; 2503 uint8_t cmd_id; 2504 uint8_t reserved1; 2505 uint16_t bad_cmd_seq_num; 2506 uint32_t error_service; 2507 uint64_t timestamp; 2508 } __packed; 2509 2510 #define IWM_FW_CMD_VER_UNKNOWN 99 2511 2512 /** 2513 * struct iwm_fw_cmd_version - firmware command version entry 2514 * @cmd: command ID 2515 * @group: group ID 2516 * @cmd_ver: command version 2517 * @notif_ver: notification version 2518 */ 2519 struct iwm_fw_cmd_version { 2520 uint8_t cmd; 2521 uint8_t group; 2522 uint8_t cmd_ver; 2523 uint8_t notif_ver; 2524 } __packed; 2525 2526 2527 /* Common PHY, MAC and Bindings definitions */ 2528 2529 #define IWM_MAX_MACS_IN_BINDING (3) 2530 #define IWM_MAX_BINDINGS (4) 2531 #define IWM_AUX_BINDING_INDEX (3) 2532 #define IWM_MAX_PHYS (4) 2533 2534 /* Used to extract ID and color from the context dword */ 2535 #define IWM_FW_CTXT_ID_POS (0) 2536 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2537 #define IWM_FW_CTXT_COLOR_POS (8) 2538 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2539 #define IWM_FW_CTXT_INVALID (0xffffffff) 2540 2541 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2542 (_color << IWM_FW_CTXT_COLOR_POS)) 2543 2544 /* Possible actions on PHYs, MACs and Bindings */ 2545 enum { 2546 IWM_FW_CTXT_ACTION_STUB = 0, 2547 IWM_FW_CTXT_ACTION_ADD, 2548 IWM_FW_CTXT_ACTION_MODIFY, 2549 IWM_FW_CTXT_ACTION_REMOVE, 2550 IWM_FW_CTXT_ACTION_NUM 2551 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2552 2553 /* Time Events */ 2554 2555 /* Time Event types, according to MAC type */ 2556 enum iwm_time_event_type { 2557 /* BSS Station Events */ 2558 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2559 IWM_TE_BSS_STA_ASSOC, 2560 IWM_TE_BSS_EAP_DHCP_PROT, 2561 IWM_TE_BSS_QUIET_PERIOD, 2562 2563 /* P2P Device Events */ 2564 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2565 IWM_TE_P2P_DEVICE_LISTEN, 2566 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2567 IWM_TE_P2P_DEVICE_FULL_SCAN, 2568 2569 /* P2P Client Events */ 2570 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2571 IWM_TE_P2P_CLIENT_ASSOC, 2572 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2573 2574 /* P2P GO Events */ 2575 IWM_TE_P2P_GO_ASSOC_PROT, 2576 IWM_TE_P2P_GO_REPETITIVE_NOA, 2577 IWM_TE_P2P_GO_CT_WINDOW, 2578 2579 /* WiDi Sync Events */ 2580 IWM_TE_WIDI_TX_SYNC, 2581 2582 IWM_TE_MAX 2583 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2584 2585 2586 2587 /* Time event - defines for command API v1 */ 2588 2589 /* 2590 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2591 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2592 * the first fragment is scheduled. 2593 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2594 * the first 2 fragments are scheduled. 2595 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2596 * number of fragments are valid. 2597 * 2598 * Other than the constant defined above, specifying a fragmentation value 'x' 2599 * means that the event can be fragmented but only the first 'x' will be 2600 * scheduled. 2601 */ 2602 enum { 2603 IWM_TE_V1_FRAG_NONE = 0, 2604 IWM_TE_V1_FRAG_SINGLE = 1, 2605 IWM_TE_V1_FRAG_DUAL = 2, 2606 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2607 }; 2608 2609 /* If a Time Event can be fragmented, this is the max number of fragments */ 2610 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2611 /* Repeat the time event endlessly (until removed) */ 2612 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2613 /* If a Time Event has bounded repetitions, this is the maximal value */ 2614 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2615 2616 /* Time Event dependencies: none, on another TE, or in a specific time */ 2617 enum { 2618 IWM_TE_V1_INDEPENDENT = 0, 2619 IWM_TE_V1_DEP_OTHER = (1 << 0), 2620 IWM_TE_V1_DEP_TSF = (1 << 1), 2621 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2622 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2623 2624 /* 2625 * @IWM_TE_V1_NOTIF_NONE: no notifications 2626 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2627 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2628 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2629 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2630 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2631 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2632 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2633 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2634 * 2635 * Supported Time event notifications configuration. 2636 * A notification (both event and fragment) includes a status indicating weather 2637 * the FW was able to schedule the event or not. For fragment start/end 2638 * notification the status is always success. There is no start/end fragment 2639 * notification for monolithic events. 2640 */ 2641 enum { 2642 IWM_TE_V1_NOTIF_NONE = 0, 2643 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2644 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2645 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2646 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2647 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2648 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2649 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2650 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2651 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2652 2653 2654 /** 2655 * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2656 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2657 * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2658 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2659 * @id_and_color: ID and color of the relevant MAC 2660 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2661 * @id: this field has two meanings, depending on the action: 2662 * If the action is ADD, then it means the type of event to add. 2663 * For all other actions it is the unique event ID assigned when the 2664 * event was added by the FW. 2665 * @apply_time: When to start the Time Event (in GP2) 2666 * @max_delay: maximum delay to event's start (apply time), in TU 2667 * @depends_on: the unique ID of the event we depend on (if any) 2668 * @interval: interval between repetitions, in TU 2669 * @interval_reciprocal: 2^32 / interval 2670 * @duration: duration of event in TU 2671 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2672 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2673 * and IWM_TE_V1_EVENT_SOCIOPATHIC 2674 * @is_present: 0 or 1, are we present or absent during the Time Event 2675 * @max_frags: maximal number of fragments the Time Event can be divided to 2676 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2677 */ 2678 struct iwm_time_event_cmd_v1 { 2679 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2680 uint32_t id_and_color; 2681 uint32_t action; 2682 uint32_t id; 2683 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2684 uint32_t apply_time; 2685 uint32_t max_delay; 2686 uint32_t dep_policy; 2687 uint32_t depends_on; 2688 uint32_t is_present; 2689 uint32_t max_frags; 2690 uint32_t interval; 2691 uint32_t interval_reciprocal; 2692 uint32_t duration; 2693 uint32_t repeat; 2694 uint32_t notify; 2695 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2696 2697 2698 /* Time event - defines for command API v2 */ 2699 2700 /** 2701 * DOC: Time Events - what is it? 2702 * 2703 * Time Events are a fw feature that allows the driver to control the presence 2704 * of the device on the channel. Since the fw supports multiple channels 2705 * concurrently, the fw may choose to jump to another channel at any time. 2706 * In order to make sure that the fw is on a specific channel at a certain time 2707 * and for a certain duration, the driver needs to issue a time event. 2708 * 2709 * The simplest example is for BSS association. The driver issues a time event, 2710 * waits for it to start, and only then tells mac80211 that we can start the 2711 * association. This way, we make sure that the association will be done 2712 * smoothly and won't be interrupted by channel switch decided within the fw. 2713 */ 2714 2715 /** 2716 * DOC: The flow against the fw 2717 * 2718 * When the driver needs to make sure we are in a certain channel, at a certain 2719 * time and for a certain duration, it sends a Time Event. The flow against the 2720 * fw goes like this: 2721 * 1) Driver sends a TIME_EVENT_CMD to the fw 2722 * 2) Driver gets the response for that command. This response contains the 2723 * Unique ID (UID) of the event. 2724 * 3) The fw sends notification when the event starts. 2725 * 2726 * Of course the API provides various options that allow to cover parameters 2727 * of the flow. 2728 * What is the duration of the event? 2729 * What is the start time of the event? 2730 * Is there an end-time for the event? 2731 * How much can the event be delayed? 2732 * Can the event be split? 2733 * If yes what is the maximal number of chunks? 2734 * etc... 2735 */ 2736 2737 /* 2738 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2739 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2740 * the first fragment is scheduled. 2741 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2742 * the first 2 fragments are scheduled. 2743 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2744 * number of fragments are valid. 2745 * 2746 * Other than the constant defined above, specifying a fragmentation value 'x' 2747 * means that the event can be fragmented but only the first 'x' will be 2748 * scheduled. 2749 */ 2750 enum { 2751 IWM_TE_V2_FRAG_NONE = 0, 2752 IWM_TE_V2_FRAG_SINGLE = 1, 2753 IWM_TE_V2_FRAG_DUAL = 2, 2754 IWM_TE_V2_FRAG_MAX = 0xfe, 2755 IWM_TE_V2_FRAG_ENDLESS = 0xff 2756 }; 2757 2758 /* Repeat the time event endlessly (until removed) */ 2759 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2760 /* If a Time Event has bounded repetitions, this is the maximal value */ 2761 #define IWM_TE_V2_REPEAT_MAX 0xfe 2762 2763 #define IWM_TE_V2_PLACEMENT_POS 12 2764 #define IWM_TE_V2_ABSENCE_POS 15 2765 2766 /* Time event policy values (for time event cmd api v2) 2767 * A notification (both event and fragment) includes a status indicating weather 2768 * the FW was able to schedule the event or not. For fragment start/end 2769 * notification the status is always success. There is no start/end fragment 2770 * notification for monolithic events. 2771 * 2772 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unnoticeable 2773 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2774 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2775 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2776 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2777 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2778 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2779 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2780 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2781 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2782 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2783 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2784 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2785 */ 2786 enum { 2787 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2788 2789 /* notifications (event start/stop, fragment start/stop) */ 2790 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2791 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2792 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2793 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2794 2795 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2796 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2797 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2798 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2799 IWM_TE_V2_START_IMMEDIATELY = (1 << 11), 2800 2801 IWM_TE_V2_NOTIF_MSK = 0xff, 2802 2803 /* placement characteristics */ 2804 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2805 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2806 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2807 2808 /* are we present or absent during the Time Event. */ 2809 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2810 }; 2811 2812 /** 2813 * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2814 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2815 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2816 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2817 * @id_and_color: ID and color of the relevant MAC 2818 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2819 * @id: this field has two meanings, depending on the action: 2820 * If the action is ADD, then it means the type of event to add. 2821 * For all other actions it is the unique event ID assigned when the 2822 * event was added by the FW. 2823 * @apply_time: When to start the Time Event (in GP2) 2824 * @max_delay: maximum delay to event's start (apply time), in TU 2825 * @depends_on: the unique ID of the event we depend on (if any) 2826 * @interval: interval between repetitions, in TU 2827 * @duration: duration of event in TU 2828 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2829 * @max_frags: maximal number of fragments the Time Event can be divided to 2830 * @policy: defines whether uCode shall notify the host or other uCode modules 2831 * on event and/or fragment start and/or end 2832 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2833 * IWM_TE_EVENT_SOCIOPATHIC 2834 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2835 */ 2836 struct iwm_time_event_cmd { 2837 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2838 uint32_t id_and_color; 2839 uint32_t action; 2840 uint32_t id; 2841 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2842 uint32_t apply_time; 2843 uint32_t max_delay; 2844 uint32_t depends_on; 2845 uint32_t interval; 2846 uint32_t duration; 2847 uint8_t repeat; 2848 uint8_t max_frags; 2849 uint16_t policy; 2850 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2851 2852 /** 2853 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2854 * @status: bit 0 indicates success, all others specify errors 2855 * @id: the Time Event type 2856 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2857 * @id_and_color: ID and color of the relevant MAC 2858 */ 2859 struct iwm_time_event_resp { 2860 uint32_t status; 2861 uint32_t id; 2862 uint32_t unique_id; 2863 uint32_t id_and_color; 2864 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2865 2866 /** 2867 * struct iwm_time_event_notif - notifications of time event start/stop 2868 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2869 * @timestamp: action timestamp in GP2 2870 * @session_id: session's unique id 2871 * @unique_id: unique id of the Time Event itself 2872 * @id_and_color: ID and color of the relevant MAC 2873 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2874 * @status: true if scheduled, false otherwise (not executed) 2875 */ 2876 struct iwm_time_event_notif { 2877 uint32_t timestamp; 2878 uint32_t session_id; 2879 uint32_t unique_id; 2880 uint32_t id_and_color; 2881 uint32_t action; 2882 uint32_t status; 2883 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2884 2885 2886 /* Bindings and Time Quota */ 2887 2888 /** 2889 * struct iwm_binding_cmd_v1 - configuring bindings 2890 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2891 * @id_and_color: ID and color of the relevant Binding 2892 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2893 * @macs: array of MAC id and colors which belong to the binding 2894 * @phy: PHY id and color which belongs to the binding 2895 * @lmac_id: the lmac id the binding belongs to 2896 */ 2897 struct iwm_binding_cmd_v1 { 2898 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2899 uint32_t id_and_color; 2900 uint32_t action; 2901 /* IWM_BINDING_DATA_API_S_VER_1 */ 2902 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2903 uint32_t phy; 2904 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2905 2906 /** 2907 * struct iwm_binding_cmd - configuring bindings 2908 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2909 * @id_and_color: ID and color of the relevant Binding 2910 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2911 * @macs: array of MAC id and colors which belong to the binding 2912 * @phy: PHY id and color which belongs to the binding 2913 */ 2914 struct iwm_binding_cmd { 2915 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2916 uint32_t id_and_color; 2917 uint32_t action; 2918 /* IWM_BINDING_DATA_API_S_VER_1 */ 2919 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2920 uint32_t phy; 2921 uint32_t lmac_id; 2922 } __packed; /* IWM_BINDING_CMD_API_S_VER_2 */ 2923 2924 #define IWM_LMAC_24G_INDEX 0 2925 #define IWM_LMAC_5G_INDEX 1 2926 2927 /* The maximal number of fragments in the FW's schedule session */ 2928 #define IWM_MAX_QUOTA 128 2929 2930 /** 2931 * struct iwm_time_quota_data - configuration of time quota per binding 2932 * @id_and_color: ID and color of the relevant Binding 2933 * @quota: absolute time quota in TU. The scheduler will try to divide the 2934 * remainig quota (after Time Events) according to this quota. 2935 * @max_duration: max uninterrupted context duration in TU 2936 */ 2937 struct iwm_time_quota_data { 2938 uint32_t id_and_color; 2939 uint32_t quota; 2940 uint32_t max_duration; 2941 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2942 2943 /** 2944 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2945 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2946 * @quotas: allocations per binding 2947 */ 2948 struct iwm_time_quota_cmd { 2949 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2950 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2951 2952 2953 /* PHY context */ 2954 2955 /* Supported bands */ 2956 #define IWM_PHY_BAND_5 (0) 2957 #define IWM_PHY_BAND_24 (1) 2958 2959 /* Supported channel width, vary if there is VHT support */ 2960 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2961 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2962 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2963 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2964 2965 /* 2966 * Control channel position: 2967 * For legacy set bit means upper channel, otherwise lower. 2968 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2969 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2970 * center_freq 2971 * | 2972 * 40Mhz |_______|_______| 2973 * 80Mhz |_______|_______|_______|_______| 2974 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2975 * code 011 010 001 000 | 100 101 110 111 2976 */ 2977 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2978 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2979 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2980 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2981 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2982 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2983 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2984 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2985 2986 /* 2987 * @band: IWM_PHY_BAND_* 2988 * @channel: channel number 2989 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2990 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2991 */ 2992 struct iwm_fw_channel_info_v1 { 2993 uint8_t band; 2994 uint8_t channel; 2995 uint8_t width; 2996 uint8_t ctrl_pos; 2997 } __packed; 2998 2999 /* 3000 * struct iwm_fw_channel_info - channel information 3001 * 3002 * @channel: channel number 3003 * @band: PHY_BAND_* 3004 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 3005 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 3006 * @reserved: for future use and alignment 3007 */ 3008 struct iwm_fw_channel_info { 3009 uint32_t channel; 3010 uint8_t band; 3011 uint8_t width; 3012 uint8_t ctrl_pos; 3013 uint8_t reserved; 3014 } __packed; /* CHANNEL_CONFIG_API_S_VER_2 */ 3015 3016 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 3017 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 3018 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 3019 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 3020 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 3021 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 3022 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 3023 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 3024 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 3025 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 3026 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 3027 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 3028 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 3029 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 3030 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 3031 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 3032 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 3033 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 3034 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 3035 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 3036 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 3037 3038 /* TODO: fix the value, make it depend on firmware at runtime? */ 3039 #define IWM_NUM_PHY_CTX 3 3040 3041 /* TODO: complete missing documentation */ 3042 /** 3043 * struct iwm_phy_context_cmd - config of the PHY context 3044 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 3045 * @id_and_color: ID and color of the relevant Binding 3046 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3047 * @apply_time: 0 means immediate apply and context switch. 3048 * other value means apply new params after X usecs 3049 * @tx_param_color: ??? 3050 * @channel_info: 3051 * @txchain_info: ??? 3052 * @rxchain_info: ??? 3053 * @acquisition_data: ??? 3054 * @dsp_cfg_flags: set to 0 3055 */ 3056 /* 3057 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased 3058 * the size of fw_channel_info from v1 to v2. 3059 * To keep things simple we define two versions of this struct, and both 3060 * are labeled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark 3061 * magic with pointers to struct members instead.) 3062 */ 3063 /* This version must be used if IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */ 3064 struct iwm_phy_context_cmd_uhb { 3065 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3066 uint32_t id_and_color; 3067 uint32_t action; 3068 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 3069 uint32_t apply_time; 3070 uint32_t tx_param_color; 3071 struct iwm_fw_channel_info ci; 3072 uint32_t txchain_info; 3073 uint32_t rxchain_info; 3074 uint32_t acquisition_data; 3075 uint32_t dsp_cfg_flags; 3076 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 3077 /* This version must be used otherwise: */ 3078 struct iwm_phy_context_cmd { 3079 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3080 uint32_t id_and_color; 3081 uint32_t action; 3082 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 3083 uint32_t apply_time; 3084 uint32_t tx_param_color; 3085 struct iwm_fw_channel_info_v1 ci; 3086 uint32_t txchain_info; 3087 uint32_t rxchain_info; 3088 uint32_t acquisition_data; 3089 uint32_t dsp_cfg_flags; 3090 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 3091 3092 #define IWM_RX_INFO_PHY_CNT 8 3093 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 3094 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 3095 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 3096 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 3097 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 3098 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 3099 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 3100 3101 #define IWM_RX_INFO_AGC_IDX 1 3102 #define IWM_RX_INFO_RSSI_AB_IDX 2 3103 #define IWM_OFDM_AGC_A_MSK 0x0000007f 3104 #define IWM_OFDM_AGC_A_POS 0 3105 #define IWM_OFDM_AGC_B_MSK 0x00003f80 3106 #define IWM_OFDM_AGC_B_POS 7 3107 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 3108 #define IWM_OFDM_AGC_CODE_POS 20 3109 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 3110 #define IWM_OFDM_RSSI_A_POS 0 3111 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 3112 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 3113 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 3114 #define IWM_OFDM_RSSI_B_POS 16 3115 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 3116 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 3117 3118 /** 3119 * struct iwm_rx_phy_info - phy info 3120 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 3121 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 3122 * @cfg_phy_cnt: configurable DSP phy data byte count 3123 * @stat_id: configurable DSP phy data set ID 3124 * @reserved1: 3125 * @system_timestamp: GP2 at on air rise 3126 * @timestamp: TSF at on air rise 3127 * @beacon_time_stamp: beacon at on-air rise 3128 * @phy_flags: general phy flags: band, modulation, ... 3129 * @channel: channel number 3130 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 3131 * @rate_n_flags: IWM_RATE_MCS_* 3132 * @byte_count: frame's byte-count 3133 * @frame_time: frame's time on the air, based on byte count and frame rate 3134 * calculation 3135 * @mac_active_msk: what MACs were active when the frame was received 3136 * 3137 * Before each Rx, the device sends this data. It contains PHY information 3138 * about the reception of the packet. 3139 */ 3140 struct iwm_rx_phy_info { 3141 uint8_t non_cfg_phy_cnt; 3142 uint8_t cfg_phy_cnt; 3143 uint8_t stat_id; 3144 uint8_t reserved1; 3145 uint32_t system_timestamp; 3146 uint64_t timestamp; 3147 uint32_t beacon_time_stamp; 3148 uint16_t phy_flags; 3149 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 3150 uint16_t channel; 3151 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 3152 uint32_t rate_n_flags; 3153 uint32_t byte_count; 3154 uint16_t mac_active_msk; 3155 uint16_t frame_time; 3156 } __packed; 3157 3158 struct iwm_rx_mpdu_res_start { 3159 uint16_t byte_count; 3160 uint16_t reserved; 3161 } __packed; 3162 3163 /** 3164 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 3165 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 3166 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 3167 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 3168 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 3169 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 3170 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 3171 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 3172 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 3173 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 3174 */ 3175 enum iwm_rx_phy_flags { 3176 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 3177 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 3178 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 3179 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 3180 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 3181 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 3182 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 3183 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 3184 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 3185 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 3186 }; 3187 3188 /** 3189 * enum iwm_mvm_rx_status - written by fw for each Rx packet 3190 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 3191 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 3192 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 3193 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 3194 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 3195 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 3196 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 3197 * in the driver. 3198 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 3199 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 3200 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 3201 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 3202 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 3203 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 3204 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 3205 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 3206 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 3207 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 3208 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 3209 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 3210 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 3211 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 3212 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 3213 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 3214 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 3215 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 3216 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 3217 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 3218 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 3219 */ 3220 enum iwm_mvm_rx_status { 3221 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 3222 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 3223 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 3224 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 3225 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 3226 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 3227 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 3228 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 3229 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 3230 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 3231 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 3232 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 3233 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 3234 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 3235 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 3236 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 3237 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 3238 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 3239 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 3240 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 3241 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 3242 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 3243 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 3244 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 3245 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 3246 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 3247 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 3248 }; 3249 3250 /** 3251 * struct iwm_radio_version_notif - information on the radio version 3252 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 3253 * @radio_flavor: 3254 * @radio_step: 3255 * @radio_dash: 3256 */ 3257 struct iwm_radio_version_notif { 3258 uint32_t radio_flavor; 3259 uint32_t radio_step; 3260 uint32_t radio_dash; 3261 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 3262 3263 enum iwm_card_state_flags { 3264 IWM_CARD_ENABLED = 0x00, 3265 IWM_HW_CARD_DISABLED = 0x01, 3266 IWM_SW_CARD_DISABLED = 0x02, 3267 IWM_CT_KILL_CARD_DISABLED = 0x04, 3268 IWM_HALT_CARD_DISABLED = 0x08, 3269 IWM_CARD_DISABLED_MSK = 0x0f, 3270 IWM_CARD_IS_RX_ON = 0x10, 3271 }; 3272 3273 /** 3274 * struct iwm_radio_version_notif - information on the radio version 3275 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 3276 * @flags: %iwm_card_state_flags 3277 */ 3278 struct iwm_card_state_notif { 3279 uint32_t flags; 3280 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 3281 3282 /** 3283 * struct iwm_missed_beacons_notif - information on missed beacons 3284 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 3285 * @mac_id: interface ID 3286 * @consec_missed_beacons_since_last_rx: number of consecutive missed 3287 * beacons since last RX. 3288 * @consec_missed_beacons: number of consecutive missed beacons 3289 * @num_expected_beacons: 3290 * @num_recvd_beacons: 3291 */ 3292 struct iwm_missed_beacons_notif { 3293 uint32_t mac_id; 3294 uint32_t consec_missed_beacons_since_last_rx; 3295 uint32_t consec_missed_beacons; 3296 uint32_t num_expected_beacons; 3297 uint32_t num_recvd_beacons; 3298 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 3299 3300 /** 3301 * struct iwm_mfuart_load_notif - mfuart image version & status 3302 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 3303 * @installed_ver: installed image version 3304 * @external_ver: external image version 3305 * @status: MFUART loading status 3306 * @duration: MFUART loading time 3307 */ 3308 struct iwm_mfuart_load_notif { 3309 uint32_t installed_ver; 3310 uint32_t external_ver; 3311 uint32_t status; 3312 uint32_t duration; 3313 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 3314 3315 /** 3316 * struct iwm_set_calib_default_cmd - set default value for calibration. 3317 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 3318 * @calib_index: the calibration to set value for 3319 * @length: of data 3320 * @data: the value to set for the calibration result 3321 */ 3322 struct iwm_set_calib_default_cmd { 3323 uint16_t calib_index; 3324 uint16_t length; 3325 uint8_t data[0]; 3326 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 3327 3328 #define IWM_MAX_PORT_ID_NUM 2 3329 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 3330 3331 /** 3332 * struct iwm_mcast_filter_cmd - configure multicast filter. 3333 * @filter_own: Set 1 to filter out multicast packets sent by station itself 3334 * @port_id: Multicast MAC addresses array specifier. This is a strange way 3335 * to identify network interface adopted in host-device IF. 3336 * It is used by FW as index in array of addresses. This array has 3337 * IWM_MAX_PORT_ID_NUM members. 3338 * @count: Number of MAC addresses in the array 3339 * @pass_all: Set 1 to pass all multicast packets. 3340 * @bssid: current association BSSID. 3341 * @addr_list: Place holder for array of MAC addresses. 3342 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 3343 */ 3344 struct iwm_mcast_filter_cmd { 3345 uint8_t filter_own; 3346 uint8_t port_id; 3347 uint8_t count; 3348 uint8_t pass_all; 3349 uint8_t bssid[6]; 3350 uint8_t reserved[2]; 3351 uint8_t addr_list[0]; 3352 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 3353 3354 struct iwm_statistics_dbg { 3355 uint32_t burst_check; 3356 uint32_t burst_count; 3357 uint32_t wait_for_silence_timeout_cnt; 3358 uint32_t reserved[3]; 3359 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 3360 3361 struct iwm_statistics_div { 3362 uint32_t tx_on_a; 3363 uint32_t tx_on_b; 3364 uint32_t exec_time; 3365 uint32_t probe_time; 3366 uint32_t rssi_ant; 3367 uint32_t reserved2; 3368 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3369 3370 struct iwm_statistics_general_common { 3371 uint32_t temperature; /* radio temperature */ 3372 uint32_t temperature_m; /* radio voltage */ 3373 struct iwm_statistics_dbg dbg; 3374 uint32_t sleep_time; 3375 uint32_t slots_out; 3376 uint32_t slots_idle; 3377 uint32_t ttl_timestamp; 3378 struct iwm_statistics_div div; 3379 uint32_t rx_enable_counter; 3380 /* 3381 * num_of_sos_states: 3382 * count the number of times we have to re-tune 3383 * in order to get out of bad PHY status 3384 */ 3385 uint32_t num_of_sos_states; 3386 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3387 3388 struct iwm_statistics_rx_non_phy { 3389 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3390 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3391 uint32_t non_bssid_frames; /* number of frames with BSSID that 3392 * doesn't belong to the STA BSSID */ 3393 uint32_t filtered_frames; /* count frames that were dumped in the 3394 * filtering process */ 3395 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3396 * our serving channel */ 3397 uint32_t channel_beacons; /* beacons with our bss id and in our 3398 * serving channel */ 3399 uint32_t num_missed_bcon; /* number of missed beacons */ 3400 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3401 * ADC was in saturation */ 3402 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3403 * for INA */ 3404 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3405 uint32_t interference_data_flag; /* flag for interference data 3406 * availability. 1 when data is 3407 * available. */ 3408 uint32_t channel_load; /* counts RX Enable time in uSec */ 3409 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3410 * and CCK) counter */ 3411 uint32_t beacon_rssi_a; 3412 uint32_t beacon_rssi_b; 3413 uint32_t beacon_rssi_c; 3414 uint32_t beacon_energy_a; 3415 uint32_t beacon_energy_b; 3416 uint32_t beacon_energy_c; 3417 uint32_t num_bt_kills; 3418 uint32_t mac_id; 3419 uint32_t directed_data_mpdu; 3420 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3421 3422 struct iwm_statistics_rx_phy { 3423 uint32_t ina_cnt; 3424 uint32_t fina_cnt; 3425 uint32_t plcp_err; 3426 uint32_t crc32_err; 3427 uint32_t overrun_err; 3428 uint32_t early_overrun_err; 3429 uint32_t crc32_good; 3430 uint32_t false_alarm_cnt; 3431 uint32_t fina_sync_err_cnt; 3432 uint32_t sfd_timeout; 3433 uint32_t fina_timeout; 3434 uint32_t unresponded_rts; 3435 uint32_t rxe_frame_limit_overrun; 3436 uint32_t sent_ack_cnt; 3437 uint32_t sent_cts_cnt; 3438 uint32_t sent_ba_rsp_cnt; 3439 uint32_t dsp_self_kill; 3440 uint32_t mh_format_err; 3441 uint32_t re_acq_main_rssi_sum; 3442 uint32_t reserved; 3443 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3444 3445 struct iwm_statistics_rx_ht_phy { 3446 uint32_t plcp_err; 3447 uint32_t overrun_err; 3448 uint32_t early_overrun_err; 3449 uint32_t crc32_good; 3450 uint32_t crc32_err; 3451 uint32_t mh_format_err; 3452 uint32_t agg_crc32_good; 3453 uint32_t agg_mpdu_cnt; 3454 uint32_t agg_cnt; 3455 uint32_t unsupport_mcs; 3456 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3457 3458 #define IWM_MAX_CHAINS 3 3459 3460 struct iwm_statistics_tx_non_phy_agg { 3461 uint32_t ba_timeout; 3462 uint32_t ba_reschedule_frames; 3463 uint32_t scd_query_agg_frame_cnt; 3464 uint32_t scd_query_no_agg; 3465 uint32_t scd_query_agg; 3466 uint32_t scd_query_mismatch; 3467 uint32_t frame_not_ready; 3468 uint32_t underrun; 3469 uint32_t bt_prio_kill; 3470 uint32_t rx_ba_rsp_cnt; 3471 int8_t txpower[IWM_MAX_CHAINS]; 3472 int8_t reserved; 3473 uint32_t reserved2; 3474 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3475 3476 struct iwm_statistics_tx_channel_width { 3477 uint32_t ext_cca_narrow_ch20[1]; 3478 uint32_t ext_cca_narrow_ch40[2]; 3479 uint32_t ext_cca_narrow_ch80[3]; 3480 uint32_t ext_cca_narrow_ch160[4]; 3481 uint32_t last_tx_ch_width_indx; 3482 uint32_t rx_detected_per_ch_width[4]; 3483 uint32_t success_per_ch_width[4]; 3484 uint32_t fail_per_ch_width[4]; 3485 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3486 3487 struct iwm_statistics_tx { 3488 uint32_t preamble_cnt; 3489 uint32_t rx_detected_cnt; 3490 uint32_t bt_prio_defer_cnt; 3491 uint32_t bt_prio_kill_cnt; 3492 uint32_t few_bytes_cnt; 3493 uint32_t cts_timeout; 3494 uint32_t ack_timeout; 3495 uint32_t expected_ack_cnt; 3496 uint32_t actual_ack_cnt; 3497 uint32_t dump_msdu_cnt; 3498 uint32_t burst_abort_next_frame_mismatch_cnt; 3499 uint32_t burst_abort_missing_next_frame_cnt; 3500 uint32_t cts_timeout_collision; 3501 uint32_t ack_or_ba_timeout_collision; 3502 struct iwm_statistics_tx_non_phy_agg agg; 3503 struct iwm_statistics_tx_channel_width channel_width; 3504 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3505 3506 3507 struct iwm_statistics_bt_activity { 3508 uint32_t hi_priority_tx_req_cnt; 3509 uint32_t hi_priority_tx_denied_cnt; 3510 uint32_t lo_priority_tx_req_cnt; 3511 uint32_t lo_priority_tx_denied_cnt; 3512 uint32_t hi_priority_rx_req_cnt; 3513 uint32_t hi_priority_rx_denied_cnt; 3514 uint32_t lo_priority_rx_req_cnt; 3515 uint32_t lo_priority_rx_denied_cnt; 3516 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3517 3518 struct iwm_statistics_general { 3519 struct iwm_statistics_general_common common; 3520 uint32_t beacon_filtered; 3521 uint32_t missed_beacons; 3522 int8_t beacon_filter_average_energy; 3523 int8_t beacon_filter_reason; 3524 int8_t beacon_filter_current_energy; 3525 int8_t beacon_filter_reserved; 3526 uint32_t beacon_filter_delta_time; 3527 struct iwm_statistics_bt_activity bt_activity; 3528 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3529 3530 struct iwm_statistics_rx { 3531 struct iwm_statistics_rx_phy ofdm; 3532 struct iwm_statistics_rx_phy cck; 3533 struct iwm_statistics_rx_non_phy general; 3534 struct iwm_statistics_rx_ht_phy ofdm_ht; 3535 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3536 3537 /* 3538 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3539 * 3540 * By default, uCode issues this notification after receiving a beacon 3541 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3542 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3543 * 3544 * Statistics counters continue to increment beacon after beacon, but are 3545 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3546 * 0x9c with CLEAR_STATS bit set (see above). 3547 * 3548 * uCode also issues this notification during scans. uCode clears statistics 3549 * appropriately so that each notification contains statistics for only the 3550 * one channel that has just been scanned. 3551 */ 3552 3553 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3554 uint32_t flag; 3555 struct iwm_statistics_rx rx; 3556 struct iwm_statistics_tx tx; 3557 struct iwm_statistics_general general; 3558 } __packed; 3559 3560 /*********************************** 3561 * Smart Fifo API 3562 ***********************************/ 3563 /* Smart Fifo state */ 3564 enum iwm_sf_state { 3565 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3566 IWM_SF_FULL_ON, 3567 IWM_SF_UNINIT, 3568 IWM_SF_INIT_OFF, 3569 IWM_SF_HW_NUM_STATES 3570 }; 3571 3572 /* Smart Fifo possible scenario */ 3573 enum iwm_sf_scenario { 3574 IWM_SF_SCENARIO_SINGLE_UNICAST, 3575 IWM_SF_SCENARIO_AGG_UNICAST, 3576 IWM_SF_SCENARIO_MULTICAST, 3577 IWM_SF_SCENARIO_BA_RESP, 3578 IWM_SF_SCENARIO_TX_RESP, 3579 IWM_SF_NUM_SCENARIO 3580 }; 3581 3582 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3583 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3584 3585 /* smart FIFO default values */ 3586 #define IWM_SF_W_MARK_SISO 4096 3587 #define IWM_SF_W_MARK_MIMO2 8192 3588 #define IWM_SF_W_MARK_MIMO3 6144 3589 #define IWM_SF_W_MARK_LEGACY 4096 3590 #define IWM_SF_W_MARK_SCAN 4096 3591 3592 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3593 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3594 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3595 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3596 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3597 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 3598 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3599 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3600 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3601 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3602 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3603 3604 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3605 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3606 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3607 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3608 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3609 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3610 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3611 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3612 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3613 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3614 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3615 3616 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3617 3618 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3619 3620 /** 3621 * Smart Fifo configuration command. 3622 * @state: smart fifo state, types listed in enum %iwm_sf_state. 3623 * @watermark: Minimum allowed available free space in RXF for transient state. 3624 * @long_delay_timeouts: aging and idle timer values for each scenario 3625 * in long delay state. 3626 * @full_on_timeouts: timer values for each scenario in full on state. 3627 */ 3628 struct iwm_sf_cfg_cmd { 3629 uint32_t state; 3630 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3631 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3632 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3633 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3634 3635 /* 3636 * The first MAC indices (starting from 0) 3637 * are available to the driver, AUX follows 3638 */ 3639 #define IWM_MAC_INDEX_AUX 4 3640 #define IWM_MAC_INDEX_MIN_DRIVER 0 3641 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3642 3643 enum iwm_ac { 3644 IWM_AC_BK, 3645 IWM_AC_BE, 3646 IWM_AC_VI, 3647 IWM_AC_VO, 3648 IWM_AC_NUM, 3649 }; 3650 3651 /** 3652 * enum iwm_mac_protection_flags - MAC context flags 3653 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3654 * this will require CCK RTS/CTS2self. 3655 * RTS/CTS will protect full burst time. 3656 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3657 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3658 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3659 */ 3660 enum iwm_mac_protection_flags { 3661 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3662 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3663 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3664 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3665 }; 3666 3667 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3668 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3669 3670 /** 3671 * enum iwm_mac_types - Supported MAC types 3672 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3673 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3674 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3675 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3676 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3677 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3678 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3679 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3680 * @IWM_FW_MAC_TYPE_GO: P2P GO 3681 * @IWM_FW_MAC_TYPE_TEST: ? 3682 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3683 */ 3684 enum iwm_mac_types { 3685 IWM_FW_MAC_TYPE_FIRST = 1, 3686 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3687 IWM_FW_MAC_TYPE_LISTENER, 3688 IWM_FW_MAC_TYPE_PIBSS, 3689 IWM_FW_MAC_TYPE_IBSS, 3690 IWM_FW_MAC_TYPE_BSS_STA, 3691 IWM_FW_MAC_TYPE_P2P_DEVICE, 3692 IWM_FW_MAC_TYPE_P2P_STA, 3693 IWM_FW_MAC_TYPE_GO, 3694 IWM_FW_MAC_TYPE_TEST, 3695 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3696 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3697 3698 /** 3699 * enum iwm_tsf_id - TSF hw timer ID 3700 * @IWM_TSF_ID_A: use TSF A 3701 * @IWM_TSF_ID_B: use TSF B 3702 * @IWM_TSF_ID_C: use TSF C 3703 * @IWM_TSF_ID_D: use TSF D 3704 * @IWM_NUM_TSF_IDS: number of TSF timers available 3705 */ 3706 enum iwm_tsf_id { 3707 IWM_TSF_ID_A = 0, 3708 IWM_TSF_ID_B = 1, 3709 IWM_TSF_ID_C = 2, 3710 IWM_TSF_ID_D = 3, 3711 IWM_NUM_TSF_IDS = 4, 3712 }; /* IWM_TSF_ID_API_E_VER_1 */ 3713 3714 /** 3715 * struct iwm_mac_data_ap - configuration data for AP MAC context 3716 * @beacon_time: beacon transmit time in system time 3717 * @beacon_tsf: beacon transmit time in TSF 3718 * @bi: beacon interval in TU 3719 * @bi_reciprocal: 2^32 / bi 3720 * @dtim_interval: dtim transmit time in TU 3721 * @dtim_reciprocal: 2^32 / dtim_interval 3722 * @mcast_qid: queue ID for multicast traffic 3723 * @beacon_template: beacon template ID 3724 */ 3725 struct iwm_mac_data_ap { 3726 uint32_t beacon_time; 3727 uint64_t beacon_tsf; 3728 uint32_t bi; 3729 uint32_t bi_reciprocal; 3730 uint32_t dtim_interval; 3731 uint32_t dtim_reciprocal; 3732 uint32_t mcast_qid; 3733 uint32_t beacon_template; 3734 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3735 3736 /** 3737 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3738 * @beacon_time: beacon transmit time in system time 3739 * @beacon_tsf: beacon transmit time in TSF 3740 * @bi: beacon interval in TU 3741 * @bi_reciprocal: 2^32 / bi 3742 * @beacon_template: beacon template ID 3743 */ 3744 struct iwm_mac_data_ibss { 3745 uint32_t beacon_time; 3746 uint64_t beacon_tsf; 3747 uint32_t bi; 3748 uint32_t bi_reciprocal; 3749 uint32_t beacon_template; 3750 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3751 3752 /** 3753 * struct iwm_mac_data_sta - configuration data for station MAC context 3754 * @is_assoc: 1 for associated state, 0 otherwise 3755 * @dtim_time: DTIM arrival time in system time 3756 * @dtim_tsf: DTIM arrival time in TSF 3757 * @bi: beacon interval in TU, applicable only when associated 3758 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3759 * @dtim_interval: DTIM interval in TU, applicable only when associated 3760 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3761 * @listen_interval: in beacon intervals, applicable only when associated 3762 * @assoc_id: unique ID assigned by the AP during association 3763 */ 3764 struct iwm_mac_data_sta { 3765 uint32_t is_assoc; 3766 uint32_t dtim_time; 3767 uint64_t dtim_tsf; 3768 uint32_t bi; 3769 uint32_t bi_reciprocal; 3770 uint32_t dtim_interval; 3771 uint32_t dtim_reciprocal; 3772 uint32_t listen_interval; 3773 uint32_t assoc_id; 3774 uint32_t assoc_beacon_arrive_time; 3775 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3776 3777 /** 3778 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3779 * @ap: iwm_mac_data_ap struct with most config data 3780 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3781 * 0 indicates that there is no CT window. 3782 * @opp_ps_enabled: indicate that opportunistic PS allowed 3783 */ 3784 struct iwm_mac_data_go { 3785 struct iwm_mac_data_ap ap; 3786 uint32_t ctwin; 3787 uint32_t opp_ps_enabled; 3788 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3789 3790 /** 3791 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3792 * @sta: iwm_mac_data_sta struct with most config data 3793 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3794 * 0 indicates that there is no CT window. 3795 */ 3796 struct iwm_mac_data_p2p_sta { 3797 struct iwm_mac_data_sta sta; 3798 uint32_t ctwin; 3799 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3800 3801 /** 3802 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3803 * @stats_interval: interval in TU between statistics notifications to host. 3804 */ 3805 struct iwm_mac_data_pibss { 3806 uint32_t stats_interval; 3807 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3808 3809 /* 3810 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3811 * context. 3812 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3813 * other channels as well. This should be to true only in case that the 3814 * device is discoverable and there is an active GO. Note that setting this 3815 * field when not needed, will increase the number of interrupts and have 3816 * effect on the platform power, as this setting opens the Rx filters on 3817 * all macs. 3818 */ 3819 struct iwm_mac_data_p2p_dev { 3820 uint32_t is_disc_extended; 3821 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3822 3823 /** 3824 * enum iwm_mac_filter_flags - MAC context filter flags 3825 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3826 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3827 * control frames to the host 3828 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3829 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3830 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3831 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3832 * (in station mode when associated) 3833 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3834 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3835 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3836 */ 3837 enum iwm_mac_filter_flags { 3838 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3839 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3840 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3841 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3842 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3843 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3844 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3845 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3846 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3847 }; 3848 3849 /** 3850 * enum iwm_mac_qos_flags - QoS flags 3851 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3852 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3853 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3854 * 3855 */ 3856 enum iwm_mac_qos_flags { 3857 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3858 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3859 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3860 }; 3861 3862 /** 3863 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3864 * @cw_min: Contention window, start value in numbers of slots. 3865 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3866 * @cw_max: Contention window, max value in numbers of slots. 3867 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3868 * @aifsn: Number of slots in Arbitration Interframe Space (before 3869 * performing random backoff timing prior to Tx). Device default 1. 3870 * @fifos_mask: FIFOs used by this MAC for this AC 3871 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3872 * 3873 * One instance of this config struct for each of 4 EDCA access categories 3874 * in struct iwm_qosparam_cmd. 3875 * 3876 * Device will automatically increase contention window by (2*CW) + 1 for each 3877 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3878 * value, to cap the CW value. 3879 */ 3880 struct iwm_ac_qos { 3881 uint16_t cw_min; 3882 uint16_t cw_max; 3883 uint8_t aifsn; 3884 uint8_t fifos_mask; 3885 uint16_t edca_txop; 3886 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3887 3888 /** 3889 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3890 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3891 * @id_and_color: ID and color of the MAC 3892 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3893 * @mac_type: one of IWM_FW_MAC_TYPE_* 3894 * @tsf_id: TSF HW timer, one of IWM_TSF_ID_* 3895 * @node_addr: MAC address 3896 * @bssid_addr: BSSID 3897 * @cck_rates: basic rates available for CCK 3898 * @ofdm_rates: basic rates available for OFDM 3899 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3900 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3901 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3902 * @filter_flags: combination of IWM_MAC_FILTER_* 3903 * @qos_flags: from IWM_MAC_QOS_FLG_* 3904 * @ac: one iwm_mac_qos configuration for each AC 3905 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3906 */ 3907 struct iwm_mac_ctx_cmd { 3908 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3909 uint32_t id_and_color; 3910 uint32_t action; 3911 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3912 uint32_t mac_type; 3913 uint32_t tsf_id; 3914 uint8_t node_addr[6]; 3915 uint16_t reserved_for_node_addr; 3916 uint8_t bssid_addr[6]; 3917 uint16_t reserved_for_bssid_addr; 3918 uint32_t cck_rates; 3919 uint32_t ofdm_rates; 3920 uint32_t protection_flags; 3921 uint32_t cck_short_preamble; 3922 uint32_t short_slot; 3923 uint32_t filter_flags; 3924 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3925 uint32_t qos_flags; 3926 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3927 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3928 union { 3929 struct iwm_mac_data_ap ap; 3930 struct iwm_mac_data_go go; 3931 struct iwm_mac_data_sta sta; 3932 struct iwm_mac_data_p2p_sta p2p_sta; 3933 struct iwm_mac_data_p2p_dev p2p_dev; 3934 struct iwm_mac_data_pibss pibss; 3935 struct iwm_mac_data_ibss ibss; 3936 }; 3937 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3938 3939 static __inline uint32_t iwm_reciprocal(uint32_t v) 3940 { 3941 if (!v) 3942 return 0; 3943 return 0xFFFFFFFF / v; 3944 } 3945 3946 #define IWM_NONQOS_SEQ_GET 0x1 3947 #define IWM_NONQOS_SEQ_SET 0x2 3948 struct iwm_nonqos_seq_query_cmd { 3949 uint32_t get_set_flag; 3950 uint32_t mac_id_n_color; 3951 uint16_t value; 3952 uint16_t reserved; 3953 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3954 3955 /* Power Management Commands, Responses, Notifications */ 3956 3957 /** 3958 * masks for LTR config command flags 3959 * @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 3960 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 3961 * memory access 3962 * @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 3963 * reg change 3964 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 3965 * D0 to D3 3966 * @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 3967 * @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 3968 * @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 3969 */ 3970 #define IWM_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001 3971 #define IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002 3972 #define IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004 3973 #define IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008 3974 #define IWM_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010 3975 #define IWM_LTR_CFG_FLAG_SW_SET_LONG 0x00000020 3976 #define IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040 3977 3978 /** 3979 * struct iwm_ltr_config_cmd_v1 - configures the LTR 3980 * @flags: See %enum iwm_ltr_config_flags 3981 */ 3982 struct iwm_ltr_config_cmd_v1 { 3983 uint32_t flags; 3984 uint32_t static_long; 3985 uint32_t static_short; 3986 } __packed; /* LTR_CAPABLE_API_S_VER_1 */ 3987 3988 #define IWM_LTR_VALID_STATES_NUM 4 3989 3990 /** 3991 * struct iwm_ltr_config_cmd - configures the LTR 3992 * @flags: See %enum iwm_ltr_config_flags 3993 * @static_long: 3994 * @static_short: 3995 * @ltr_cfg_values: 3996 * @ltr_short_idle_timeout: 3997 */ 3998 struct iwm_ltr_config_cmd { 3999 uint32_t flags; 4000 uint32_t static_long; 4001 uint32_t static_short; 4002 uint32_t ltr_cfg_values[IWM_LTR_VALID_STATES_NUM]; 4003 uint32_t ltr_short_idle_timeout; 4004 } __packed; /* LTR_CAPABLE_API_S_VER_2 */ 4005 4006 /* Radio LP RX Energy Threshold measured in dBm */ 4007 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 4008 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 4009 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 4010 4011 /** 4012 * enum iwm_scan_flags - masks for iwm_mac_power_cmd command flags 4013 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 4014 * receiver and transmitter. '0' - does not allow. 4015 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 4016 * '1' Driver enables PM (use rest of parameters) 4017 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 4018 * '1' PM could sleep over DTIM till listen Interval. 4019 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 4020 * access categories are both delivery and trigger enabled. 4021 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 4022 * PBW Snoozing enabled 4023 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 4024 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 4025 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 4026 * detection enablement 4027 */ 4028 enum iwm_power_flags { 4029 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 4030 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 4031 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 4032 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 4033 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 4034 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 4035 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 4036 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 4037 }; 4038 4039 #define IWM_POWER_VEC_SIZE 5 4040 4041 /** 4042 * enum iwm_device_power_flags - masks for device power command flags 4043 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: 4044 * '1' Allow to save power by turning off receiver and transmitter. 4045 * '0' Do not allow. This flag should be always set to '1' unless 4046 * one needs to disable actual power down for debug purposes. 4047 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: 4048 * '1' CAM (Continuous Active Mode) is set, power management is disabled. 4049 * '0' Power management is enabled, one of the power schemes is applied. 4050 */ 4051 enum iwm_device_power_flags { 4052 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 4053 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 4054 }; 4055 4056 /** 4057 * struct iwm_device_power_cmd - device wide power command. 4058 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 4059 * 4060 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 4061 */ 4062 struct iwm_device_power_cmd { 4063 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 4064 uint16_t flags; 4065 uint16_t reserved; 4066 } __packed; 4067 4068 /** 4069 * struct iwm_mac_power_cmd - New power command containing uAPSD support 4070 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 4071 * @id_and_color: MAC contex identifier 4072 * @flags: Power table command flags from POWER_FLAGS_* 4073 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 4074 * Minimum allowed:- 3 * DTIM. Keep alive period must be 4075 * set regardless of power scheme or current power state. 4076 * FW use this value also when PM is disabled. 4077 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 4078 * PSM transition - legacy PM 4079 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 4080 * PSM transition - legacy PM 4081 * @sleep_interval: not in use 4082 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 4083 * is set. For example, if it is required to skip over 4084 * one DTIM, this value need to be set to 2 (DTIM periods). 4085 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 4086 * PSM transition - uAPSD 4087 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 4088 * PSM transition - uAPSD 4089 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 4090 * Default: 80dbm 4091 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 4092 * @snooze_interval: Maximum time between attempts to retrieve buffered data 4093 * from the AP [msec] 4094 * @snooze_window: A window of time in which PBW snoozing insures that all 4095 * packets received. It is also the minimum time from last 4096 * received unicast RX packet, before client stops snoozing 4097 * for data. [msec] 4098 * @snooze_step: TBD 4099 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 4100 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 4101 * each corresponding AC. 4102 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 4103 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 4104 * values. 4105 * @heavy_tx_thld_packets: TX threshold measured in number of packets 4106 * @heavy_rx_thld_packets: RX threshold measured in number of packets 4107 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 4108 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 4109 * @limited_ps_threshold: 4110 */ 4111 struct iwm_mac_power_cmd { 4112 /* CONTEXT_DESC_API_T_VER_1 */ 4113 uint32_t id_and_color; 4114 4115 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 4116 uint16_t flags; 4117 uint16_t keep_alive_seconds; 4118 uint32_t rx_data_timeout; 4119 uint32_t tx_data_timeout; 4120 uint32_t rx_data_timeout_uapsd; 4121 uint32_t tx_data_timeout_uapsd; 4122 uint8_t lprx_rssi_threshold; 4123 uint8_t skip_dtim_periods; 4124 uint16_t snooze_interval; 4125 uint16_t snooze_window; 4126 uint8_t snooze_step; 4127 uint8_t qndp_tid; 4128 uint8_t uapsd_ac_flags; 4129 uint8_t uapsd_max_sp; 4130 uint8_t heavy_tx_thld_packets; 4131 uint8_t heavy_rx_thld_packets; 4132 uint8_t heavy_tx_thld_percentage; 4133 uint8_t heavy_rx_thld_percentage; 4134 uint8_t limited_ps_threshold; 4135 uint8_t reserved; 4136 } __packed; 4137 4138 #define IWM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000) 4139 #define IWM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000) 4140 4141 /* 4142 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 4143 * associated AP is identified as improperly implementing uAPSD protocol. 4144 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 4145 * @sta_id: index of station in uCode's station table - associated AP ID in 4146 * this context. 4147 */ 4148 struct iwm_uapsd_misbehaving_ap_notif { 4149 uint32_t sta_id; 4150 uint8_t mac_id; 4151 uint8_t reserved[3]; 4152 } __packed; 4153 4154 /** 4155 * struct iwm_beacon_filter_cmd 4156 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 4157 * @id_and_color: MAC contex identifier 4158 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 4159 * to driver if delta in Energy values calculated for this and last 4160 * passed beacon is greater than this threshold. Zero value means that 4161 * the Energy change is ignored for beacon filtering, and beacon will 4162 * not be forced to be sent to driver regardless of this delta. Typical 4163 * energy delta 5dB. 4164 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 4165 * Send beacon to driver if delta in Energy values calculated for this 4166 * and last passed beacon is greater than this threshold. Zero value 4167 * means that the Energy change is ignored for beacon filtering while in 4168 * Roaming state, typical energy delta 1dB. 4169 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 4170 * calculated for current beacon is less than the threshold, use 4171 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 4172 * Threshold. Typical energy threshold is -72dBm. 4173 * @bf_temp_threshold: This threshold determines the type of temperature 4174 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 4175 * If the current temperature is above this threshold - Fast filter 4176 * will be used, If the current temperature is below this threshold - 4177 * Slow filter will be used. 4178 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 4179 * calculated for this and the last passed beacon is greater than this 4180 * threshold. Zero value means that the temperature change is ignored for 4181 * beacon filtering; beacons will not be forced to be sent to driver 4182 * regardless of whether its temerature has been changed. 4183 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 4184 * calculated for this and the last passed beacon is greater than this 4185 * threshold. Zero value means that the temperature change is ignored for 4186 * beacon filtering; beacons will not be forced to be sent to driver 4187 * regardless of whether its temerature has been changed. 4188 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 4189 * @bf_escape_timer: Send beacons to driver if no beacons were passed 4190 * for a specific period of time. Units: Beacons. 4191 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 4192 * for a longer period of time then this escape-timeout. Units: Beacons. 4193 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 4194 */ 4195 struct iwm_beacon_filter_cmd { 4196 uint32_t bf_energy_delta; 4197 uint32_t bf_roaming_energy_delta; 4198 uint32_t bf_roaming_state; 4199 uint32_t bf_temp_threshold; 4200 uint32_t bf_temp_fast_filter; 4201 uint32_t bf_temp_slow_filter; 4202 uint32_t bf_enable_beacon_filter; 4203 uint32_t bf_debug_flag; 4204 uint32_t bf_escape_timer; 4205 uint32_t ba_escape_timer; 4206 uint32_t ba_enable_beacon_abort; 4207 } __packed; 4208 4209 /* Beacon filtering and beacon abort */ 4210 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 4211 #define IWM_BF_ENERGY_DELTA_MAX 255 4212 #define IWM_BF_ENERGY_DELTA_MIN 0 4213 4214 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 4215 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 4216 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 4217 4218 #define IWM_BF_ROAMING_STATE_DEFAULT 72 4219 #define IWM_BF_ROAMING_STATE_MAX 255 4220 #define IWM_BF_ROAMING_STATE_MIN 0 4221 4222 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 4223 #define IWM_BF_TEMP_THRESHOLD_MAX 255 4224 #define IWM_BF_TEMP_THRESHOLD_MIN 0 4225 4226 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 4227 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 4228 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 4229 4230 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 4231 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 4232 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 4233 4234 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 4235 4236 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 4237 4238 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 4239 #define IWM_BF_ESCAPE_TIMER_MAX 1024 4240 #define IWM_BF_ESCAPE_TIMER_MIN 0 4241 4242 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 4243 #define IWM_BA_ESCAPE_TIMER_D3 9 4244 #define IWM_BA_ESCAPE_TIMER_MAX 1024 4245 #define IWM_BA_ESCAPE_TIMER_MIN 0 4246 4247 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 4248 4249 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 4250 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 4251 .bf_roaming_energy_delta = \ 4252 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 4253 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 4254 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 4255 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 4256 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 4257 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 4258 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 4259 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 4260 4261 /* uCode API values for HT/VHT bit rates */ 4262 enum { 4263 IWM_RATE_HT_SISO_MCS_0_PLCP = 0, 4264 IWM_RATE_HT_SISO_MCS_1_PLCP = 1, 4265 IWM_RATE_HT_SISO_MCS_2_PLCP = 2, 4266 IWM_RATE_HT_SISO_MCS_3_PLCP = 3, 4267 IWM_RATE_HT_SISO_MCS_4_PLCP = 4, 4268 IWM_RATE_HT_SISO_MCS_5_PLCP = 5, 4269 IWM_RATE_HT_SISO_MCS_6_PLCP = 6, 4270 IWM_RATE_HT_SISO_MCS_7_PLCP = 7, 4271 IWM_RATE_HT_MIMO2_MCS_0_PLCP = 0x8, 4272 IWM_RATE_HT_MIMO2_MCS_1_PLCP = 0x9, 4273 IWM_RATE_HT_MIMO2_MCS_2_PLCP = 0xA, 4274 IWM_RATE_HT_MIMO2_MCS_3_PLCP = 0xB, 4275 IWM_RATE_HT_MIMO2_MCS_4_PLCP = 0xC, 4276 IWM_RATE_HT_MIMO2_MCS_5_PLCP = 0xD, 4277 IWM_RATE_HT_MIMO2_MCS_6_PLCP = 0xE, 4278 IWM_RATE_HT_MIMO2_MCS_7_PLCP = 0xF, 4279 IWM_RATE_VHT_SISO_MCS_0_PLCP = 0, 4280 IWM_RATE_VHT_SISO_MCS_1_PLCP = 1, 4281 IWM_RATE_VHT_SISO_MCS_2_PLCP = 2, 4282 IWM_RATE_VHT_SISO_MCS_3_PLCP = 3, 4283 IWM_RATE_VHT_SISO_MCS_4_PLCP = 4, 4284 IWM_RATE_VHT_SISO_MCS_5_PLCP = 5, 4285 IWM_RATE_VHT_SISO_MCS_6_PLCP = 6, 4286 IWM_RATE_VHT_SISO_MCS_7_PLCP = 7, 4287 IWM_RATE_VHT_SISO_MCS_8_PLCP = 8, 4288 IWM_RATE_VHT_SISO_MCS_9_PLCP = 9, 4289 IWM_RATE_VHT_MIMO2_MCS_0_PLCP = 0x10, 4290 IWM_RATE_VHT_MIMO2_MCS_1_PLCP = 0x11, 4291 IWM_RATE_VHT_MIMO2_MCS_2_PLCP = 0x12, 4292 IWM_RATE_VHT_MIMO2_MCS_3_PLCP = 0x13, 4293 IWM_RATE_VHT_MIMO2_MCS_4_PLCP = 0x14, 4294 IWM_RATE_VHT_MIMO2_MCS_5_PLCP = 0x15, 4295 IWM_RATE_VHT_MIMO2_MCS_6_PLCP = 0x16, 4296 IWM_RATE_VHT_MIMO2_MCS_7_PLCP = 0x17, 4297 IWM_RATE_VHT_MIMO2_MCS_8_PLCP = 0x18, 4298 IWM_RATE_VHT_MIMO2_MCS_9_PLCP = 0x19, 4299 IWM_RATE_HT_SISO_MCS_INV_PLCP, 4300 IWM_RATE_HT_MIMO2_MCS_INV_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4301 IWM_RATE_VHT_SISO_MCS_INV_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4302 IWM_RATE_VHT_MIMO2_MCS_INV_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4303 IWM_RATE_HT_SISO_MCS_8_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4304 IWM_RATE_HT_SISO_MCS_9_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4305 IWM_RATE_HT_MIMO2_MCS_8_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4306 IWM_RATE_HT_MIMO2_MCS_9_PLCP = IWM_RATE_HT_SISO_MCS_INV_PLCP, 4307 }; 4308 4309 /* 4310 * These serve as indexes into struct iwm_rate iwm_rates[IWM_RIDX_MAX]. 4311 */ 4312 enum { 4313 IWM_RATE_1M_INDEX = 0, 4314 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 4315 IWM_RATE_2M_INDEX, 4316 IWM_RATE_5M_INDEX, 4317 IWM_RATE_11M_INDEX, 4318 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 4319 IWM_RATE_6M_INDEX, 4320 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 4321 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 4322 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 4323 IWM_RATE_9M_INDEX, 4324 IWM_RATE_12M_INDEX, 4325 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 4326 IWM_RATE_MCS_8_INDEX, 4327 IWM_FIRST_HT_MIMO2_RATE = IWM_RATE_MCS_8_INDEX, 4328 IWM_RATE_18M_INDEX, 4329 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 4330 IWM_RATE_24M_INDEX, 4331 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 4332 IWM_RATE_MCS_9_INDEX, 4333 IWM_RATE_36M_INDEX, 4334 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 4335 IWM_RATE_MCS_10_INDEX, 4336 IWM_RATE_48M_INDEX, 4337 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 4338 IWM_RATE_MCS_11_INDEX, 4339 IWM_RATE_54M_INDEX, 4340 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 4341 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 4342 IWM_RATE_MCS_7_INDEX, 4343 IWM_LAST_HT_SISO_RATE = IWM_RATE_MCS_7_INDEX, 4344 IWM_RATE_MCS_12_INDEX, 4345 IWM_RATE_MCS_13_INDEX, 4346 IWM_RATE_MCS_14_INDEX, 4347 IWM_RATE_MCS_15_INDEX, 4348 IWM_LAST_HT_RATE = IWM_RATE_MCS_15_INDEX, 4349 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 4350 IWM_RATE_COUNT = IWM_LAST_HT_RATE + 1, 4351 }; 4352 4353 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 4354 4355 /* fw API values for legacy bit rates, both OFDM and CCK */ 4356 enum { 4357 IWM_RATE_6M_PLCP = 13, 4358 IWM_RATE_9M_PLCP = 15, 4359 IWM_RATE_12M_PLCP = 5, 4360 IWM_RATE_18M_PLCP = 7, 4361 IWM_RATE_24M_PLCP = 9, 4362 IWM_RATE_36M_PLCP = 11, 4363 IWM_RATE_48M_PLCP = 1, 4364 IWM_RATE_54M_PLCP = 3, 4365 IWM_RATE_1M_PLCP = 10, 4366 IWM_RATE_2M_PLCP = 20, 4367 IWM_RATE_5M_PLCP = 55, 4368 IWM_RATE_11M_PLCP = 110, 4369 IWM_RATE_INVM_PLCP = 0xff, 4370 }; 4371 4372 /* 4373 * rate_n_flags bit fields 4374 * 4375 * The 32-bit value has different layouts in the low 8 bites depending on the 4376 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 4377 * for CCK and OFDM). 4378 * 4379 * High-throughput (HT) rate format 4380 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 4381 * Very High-throughput (VHT) rate format 4382 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 4383 * Legacy OFDM rate format for bits 7:0 4384 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 4385 * Legacy CCK rate format for bits 7:0: 4386 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 4387 */ 4388 4389 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 4390 #define IWM_RATE_MCS_HT_POS 8 4391 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 4392 4393 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 4394 #define IWM_RATE_MCS_CCK_POS 9 4395 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 4396 4397 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 4398 #define IWM_RATE_MCS_VHT_POS 26 4399 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 4400 4401 4402 /* 4403 * High-throughput (HT) rate format for bits 7:0 4404 * 4405 * 2-0: MCS rate base 4406 * 0) 6 Mbps 4407 * 1) 12 Mbps 4408 * 2) 18 Mbps 4409 * 3) 24 Mbps 4410 * 4) 36 Mbps 4411 * 5) 48 Mbps 4412 * 6) 54 Mbps 4413 * 7) 60 Mbps 4414 * 4-3: 0) Single stream (SISO) 4415 * 1) Dual stream (MIMO) 4416 * 2) Triple stream (MIMO) 4417 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4418 * (bits 7-6 are zero) 4419 * 4420 * Together the low 5 bits work out to the MCS index because we don't 4421 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4422 * streams and 16-23 have three streams. We could also support MCS 32 4423 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4424 */ 4425 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4426 #define IWM_RATE_HT_MCS_NSS_POS 3 4427 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4428 4429 /* Bit 10: (1) Use Green Field preamble */ 4430 #define IWM_RATE_HT_MCS_GF_POS 10 4431 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4432 4433 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4434 4435 /* 4436 * Very High-throughput (VHT) rate format for bits 7:0 4437 * 4438 * 3-0: VHT MCS (0-9) 4439 * 5-4: number of streams - 1: 4440 * 0) Single stream (SISO) 4441 * 1) Dual stream (MIMO) 4442 * 2) Triple stream (MIMO) 4443 */ 4444 4445 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4446 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4447 #define IWM_RATE_VHT_MCS_NSS_POS 4 4448 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4449 4450 /* 4451 * Legacy OFDM rate format for bits 7:0 4452 * 4453 * 3-0: 0xD) 6 Mbps 4454 * 0xF) 9 Mbps 4455 * 0x5) 12 Mbps 4456 * 0x7) 18 Mbps 4457 * 0x9) 24 Mbps 4458 * 0xB) 36 Mbps 4459 * 0x1) 48 Mbps 4460 * 0x3) 54 Mbps 4461 * (bits 7-4 are 0) 4462 * 4463 * Legacy CCK rate format for bits 7:0: 4464 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4465 * 4466 * 6-0: 10) 1 Mbps 4467 * 20) 2 Mbps 4468 * 55) 5.5 Mbps 4469 * 110) 11 Mbps 4470 * (bit 7 is 0) 4471 */ 4472 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4473 4474 4475 /* 4476 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4477 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4478 */ 4479 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4480 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4481 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4482 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4483 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4484 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4485 4486 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4487 #define IWM_RATE_MCS_SGI_POS 13 4488 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4489 4490 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4491 #define IWM_RATE_MCS_ANT_POS 14 4492 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4493 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4494 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4495 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4496 IWM_RATE_MCS_ANT_B_MSK) 4497 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4498 IWM_RATE_MCS_ANT_C_MSK) 4499 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4500 #define IWM_RATE_MCS_ANT_NUM 3 4501 4502 /* Bit 17-18: (0) SS, (1) SS*2 */ 4503 #define IWM_RATE_MCS_STBC_POS 17 4504 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4505 4506 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4507 #define IWM_RATE_MCS_BF_POS 19 4508 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4509 4510 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4511 #define IWM_RATE_MCS_ZLF_POS 20 4512 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4513 4514 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4515 #define IWM_RATE_MCS_DUP_POS 24 4516 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4517 4518 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4519 #define IWM_RATE_MCS_LDPC_POS 27 4520 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4521 4522 4523 /* Link Quality definitions */ 4524 4525 /* # entries in rate scale table to support Tx retries */ 4526 #define IWM_LQ_MAX_RETRY_NUM 16 4527 4528 /* Link quality command flags bit fields */ 4529 4530 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4531 #define IWM_LQ_FLAG_USE_RTS_POS 0 4532 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4533 4534 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4535 #define IWM_LQ_FLAG_COLOR_POS 1 4536 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4537 4538 /* Bit 4-5: Tx RTS BW Signalling 4539 * (0) No RTS BW signalling 4540 * (1) Static BW signalling 4541 * (2) Dynamic BW signalling 4542 */ 4543 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4544 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4545 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4546 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4547 4548 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4549 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4550 */ 4551 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4552 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4553 4554 /* Antenna flags. */ 4555 #define IWM_ANT_A (1 << 0) 4556 #define IWM_ANT_B (1 << 1) 4557 #define IWM_ANT_C (1 << 2) 4558 /* Shortcuts. */ 4559 #define IWM_ANT_AB (IWM_ANT_A | IWM_ANT_B) 4560 #define IWM_ANT_BC (IWM_ANT_B | IWM_ANT_C) 4561 #define IWM_ANT_ABC (IWM_ANT_A | IWM_ANT_B | IWM_ANT_C) 4562 4563 /** 4564 * struct iwm_lq_cmd - link quality command 4565 * @sta_id: station to update 4566 * @control: not used 4567 * @flags: combination of IWM_LQ_FLAG_* 4568 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4569 * and SISO rates 4570 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4571 * Should be IWM_ANT_[ABC] 4572 * @dual_stream_ant_msk: best antennas for MIMO, combination of IWM_ANT_[ABC] 4573 * @initial_rate_index: first index from rs_table per AC category 4574 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4575 * value of 100 is one usec. Range is 100 to 8000 4576 * @agg_disable_start_th: try-count threshold for starting aggregation. 4577 * If a frame has higher try-count, it should not be selected for 4578 * starting an aggregation sequence. 4579 * @agg_frame_cnt_limit: max frame count in an aggregation. 4580 * 0: no limit 4581 * 1: no aggregation (one frame per aggregation) 4582 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4583 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4584 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4585 * @bf_params: beam forming params, currently not used 4586 */ 4587 struct iwm_lq_cmd { 4588 uint8_t sta_id; 4589 uint8_t reserved1; 4590 uint16_t control; 4591 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4592 uint8_t flags; 4593 uint8_t mimo_delim; 4594 uint8_t single_stream_ant_msk; 4595 uint8_t dual_stream_ant_msk; 4596 uint8_t initial_rate_index[IWM_AC_NUM]; 4597 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4598 uint16_t agg_time_limit; 4599 uint8_t agg_disable_start_th; 4600 uint8_t agg_frame_cnt_limit; 4601 uint32_t reserved2; 4602 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4603 uint32_t bf_params; 4604 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4605 4606 /** 4607 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4608 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4609 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4610 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4611 * Otherwise, use rate_n_flags from the TX command 4612 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4613 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4614 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4615 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4616 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4617 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4618 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4619 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4620 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4621 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4622 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4623 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4624 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4625 * Should be set for beacons and probe responses 4626 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4627 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4628 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4629 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4630 * Should be set for 26/30 length MAC headers 4631 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4632 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4633 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4634 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4635 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4636 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4637 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4638 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4639 */ 4640 enum iwm_tx_flags { 4641 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4642 IWM_TX_CMD_FLG_ACK = (1 << 3), 4643 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4644 IWM_TX_CMD_FLG_BA = (1 << 5), 4645 IWM_TX_CMD_FLG_BAR = (1 << 6), 4646 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4647 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4648 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4649 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4650 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4651 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4652 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4653 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4654 IWM_TX_CMD_FLG_TSF = (1 << 16), 4655 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4656 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4657 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4658 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4659 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4660 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4661 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4662 IWM_TX_CMD_FLG_DUR = (1 << 25), 4663 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4664 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4665 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4666 IWM_TX_CMD_FLG_HCCA_CHUNK = (1U << 31) 4667 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4668 4669 /** 4670 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4671 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4672 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4673 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4674 */ 4675 enum iwm_tx_pm_timeouts { 4676 IWM_PM_FRAME_NONE = 0, 4677 IWM_PM_FRAME_MGMT = 2, 4678 IWM_PM_FRAME_ASSOC = 3, 4679 }; 4680 4681 /* 4682 * TX command security control 4683 */ 4684 #define IWM_TX_CMD_SEC_WEP 0x01 4685 #define IWM_TX_CMD_SEC_CCM 0x02 4686 #define IWM_TX_CMD_SEC_TKIP 0x03 4687 #define IWM_TX_CMD_SEC_EXT 0x04 4688 #define IWM_TX_CMD_SEC_MSK 0x07 4689 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4690 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4691 #define IWM_TX_CMD_SEC_KEY128 0x08 4692 4693 /* TODO: how does these values are OK with only 16 bit variable??? */ 4694 /* 4695 * TX command next frame info 4696 * 4697 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4698 * bit 3 - immediate ACK required 4699 * bit 4 - rate is taken from STA table 4700 * bit 5 - frame belongs to BA stream 4701 * bit 6 - immediate BA response expected 4702 * bit 7 - unused 4703 * bits 8:15 - Station ID 4704 * bits 16:31 - rate 4705 */ 4706 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4707 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4708 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4709 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4710 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4711 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4712 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4713 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4714 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4715 4716 /* 4717 * TX command Frame life time in us - to be written in pm_frame_timeout 4718 */ 4719 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4720 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4721 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4722 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4723 4724 /* 4725 * Maximum number of HW queues the transport layer 4726 * currently supports 4727 */ 4728 #define IWM_MAX_TID_COUNT 8 4729 4730 /* 4731 * TID for non QoS frames - to be written in tid_tspec 4732 */ 4733 #define IWM_TID_NON_QOS 0 4734 #define IWM_TID_MGMT 15 4735 4736 /* 4737 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4738 */ 4739 #define IWM_DEFAULT_TX_RETRY 15 4740 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4741 #define IWM_RTS_DFAULT_RETRY_LIMIT 3 4742 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4743 #define IWM_LOW_RETRY_LIMIT 7 4744 4745 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4746 /** 4747 * struct iwm_tx_cmd - TX command struct to FW 4748 * ( IWM_TX_CMD = 0x1c ) 4749 * @len: in bytes of the payload, see below for details 4750 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4751 * Used for fragmentation and bursting, but not in 11n aggregation. 4752 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4753 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4754 * cleared. Combination of IWM_RATE_MCS_* 4755 * @sta_id: index of destination station in FW station table 4756 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4757 * @initial_rate_index: index into the rate table for initial TX attempt. 4758 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4759 * @key: security key 4760 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4761 * @life_time: frame life time (usecs??) 4762 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4763 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4764 * @dram_msb_ptr: upper bits of the scratch physical address 4765 * @rts_retry_limit: max attempts for RTS 4766 * @data_retry_limit: max attempts to send the data packet 4767 * @tid_spec: TID/tspec 4768 * @pm_frame_timeout: PM TX frame timeout 4769 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4770 * specified by HCCA protocol 4771 * 4772 * The byte count (both len and next_frame_len) includes MAC header 4773 * (24/26/30/32 bytes) 4774 * + 2 bytes pad if 26/30 header size 4775 * + 8 byte IV for CCM or TKIP (not used for WEP) 4776 * + Data payload 4777 * + 8-byte MIC (not used for CCM/WEP) 4778 * It does not include post-MAC padding, i.e., 4779 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4780 * Range of len: 14-2342 bytes. 4781 * 4782 * After the struct fields the MAC header is placed, plus any padding, 4783 * and then the actial payload. 4784 */ 4785 struct iwm_tx_cmd { 4786 uint16_t len; 4787 uint16_t next_frame_len; 4788 uint32_t tx_flags; 4789 struct { 4790 uint8_t try_cnt; 4791 uint8_t btkill_cnt; 4792 uint16_t reserved; 4793 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4794 uint32_t rate_n_flags; 4795 uint8_t sta_id; 4796 uint8_t sec_ctl; 4797 uint8_t initial_rate_index; 4798 uint8_t reserved2; 4799 uint8_t key[16]; 4800 uint16_t next_frame_flags; 4801 uint16_t reserved3; 4802 uint32_t life_time; 4803 uint32_t dram_lsb_ptr; 4804 uint8_t dram_msb_ptr; 4805 uint8_t rts_retry_limit; 4806 uint8_t data_retry_limit; 4807 uint8_t tid_tspec; 4808 uint16_t pm_frame_timeout; 4809 uint16_t driver_txop; 4810 uint8_t payload[0]; 4811 struct ieee80211_frame hdr[0]; 4812 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4813 4814 /* 4815 * TX response related data 4816 */ 4817 4818 /* 4819 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4820 * @IWM_TX_STATUS_SUCCESS: 4821 * @IWM_TX_STATUS_DIRECT_DONE: 4822 * @IWM_TX_STATUS_POSTPONE_DELAY: 4823 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4824 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4825 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4826 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4827 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4828 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4829 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4830 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4831 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4832 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4833 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4834 * @IWM_TX_STATUS_FAIL_DEST_PS: 4835 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4836 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4837 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4838 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4839 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4840 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4841 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4842 * @IWM_TX_STATUS_FAIL_FW_DROP: 4843 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4844 * STA table 4845 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4846 * @IWM_TX_MODE_MSK: 4847 * @IWM_TX_MODE_NO_BURST: 4848 * @IWM_TX_MODE_IN_BURST_SEQ: 4849 * @IWM_TX_MODE_FIRST_IN_BURST: 4850 * @IWM_TX_QUEUE_NUM_MSK: 4851 * 4852 * Valid only if frame_count =1 4853 * TODO: complete documentation 4854 */ 4855 enum iwm_tx_status { 4856 IWM_TX_STATUS_MSK = 0x000000ff, 4857 IWM_TX_STATUS_SUCCESS = 0x01, 4858 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4859 /* postpone TX */ 4860 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4861 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4862 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4863 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4864 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4865 /* abort TX */ 4866 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4867 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4868 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4869 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4870 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4871 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4872 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4873 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4874 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4875 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4876 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4877 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4878 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4879 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4880 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4881 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4882 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4883 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4884 IWM_TX_MODE_MSK = 0x00000f00, 4885 IWM_TX_MODE_NO_BURST = 0x00000000, 4886 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4887 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4888 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4889 IWM_TX_NARROW_BW_MSK = 0x00060000, 4890 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4891 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4892 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4893 }; 4894 4895 /* 4896 * enum iwm_tx_agg_status - TX aggregation status 4897 * @IWM_AGG_TX_STATE_STATUS_MSK: 4898 * @IWM_AGG_TX_STATE_TRANSMITTED: 4899 * @IWM_AGG_TX_STATE_UNDERRUN: 4900 * @IWM_AGG_TX_STATE_BT_PRIO: 4901 * @IWM_AGG_TX_STATE_FEW_BYTES: 4902 * @IWM_AGG_TX_STATE_ABORT: 4903 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4904 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4905 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4906 * @IWM_AGG_TX_STATE_SCD_QUERY: 4907 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4908 * @IWM_AGG_TX_STATE_RESPONSE: 4909 * @IWM_AGG_TX_STATE_DUMP_TX: 4910 * @IWM_AGG_TX_STATE_DELAY_TX: 4911 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4912 * occur if tx failed for this frame when it was a member of a previous 4913 * aggregation block). If rate scaling is used, retry count indicates the 4914 * rate table entry used for all frames in the new agg. 4915 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4916 * this frame 4917 * 4918 * TODO: complete documentation 4919 */ 4920 enum iwm_tx_agg_status { 4921 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4922 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4923 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4924 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4925 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4926 IWM_AGG_TX_STATE_ABORT = 0x008, 4927 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4928 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4929 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4930 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4931 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4932 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4933 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4934 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4935 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4936 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4937 }; 4938 4939 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4940 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4941 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4942 4943 /* 4944 * The mask below describes a status where we are absolutely sure that the MPDU 4945 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4946 * written the bytes to the TXE, but we know nothing about what the DSP did. 4947 */ 4948 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4949 IWM_AGG_TX_STATE_ABORT | \ 4950 IWM_AGG_TX_STATE_SCD_QUERY) 4951 4952 /* 4953 * IWM_REPLY_TX = 0x1c (response) 4954 * 4955 * This response may be in one of two slightly different formats, indicated 4956 * by the frame_count field: 4957 * 4958 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4959 * frame. Multiple attempts, at various bit rates, may have been made for 4960 * this frame. 4961 * 4962 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4963 * frames that used block-acknowledge. All frames were transmitted at 4964 * same rate. Rate scaling may have been used if first frame in this new 4965 * agg block failed in previous agg block(s). 4966 * 4967 * Note that, for aggregation, ACK (block-ack) status is not delivered 4968 * here; block-ack has not been received by the time the device records 4969 * this status. 4970 * This status relates to reasons the tx might have been blocked or aborted 4971 * within the device, rather than whether it was received successfully by 4972 * the destination station. 4973 */ 4974 4975 /** 4976 * struct iwm_agg_tx_status - per packet TX aggregation status 4977 * @status: enum iwm_tx_agg_status 4978 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4979 */ 4980 struct iwm_agg_tx_status { 4981 uint16_t status; 4982 uint16_t sequence; 4983 } __packed; 4984 4985 /* 4986 * definitions for initial rate index field 4987 * bits [3:0] initial rate index 4988 * bits [6:4] rate table color, used for the initial rate 4989 * bit-7 invalid rate indication 4990 */ 4991 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4992 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4993 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4994 4995 #define IWM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4996 #define IWM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4997 4998 /** 4999 * struct iwm_tx_resp - notifies that fw is TXing a packet 5000 * ( IWM_REPLY_TX = 0x1c ) 5001 * @frame_count: 1 no aggregation, >1 aggregation 5002 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 5003 * @failure_rts: num of failures due to unsuccessful RTS 5004 * @failure_frame: num failures due to no ACK (unused for agg) 5005 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 5006 * Tx of all the batch. IWM_RATE_MCS_* 5007 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 5008 * for agg: RTS + CTS + aggregation tx time + block-ack time. 5009 * in usec. 5010 * @pa_status: tx power info 5011 * @pa_integ_res_a: tx power info 5012 * @pa_integ_res_b: tx power info 5013 * @pa_integ_res_c: tx power info 5014 * @measurement_req_id: tx power info 5015 * @tfd_info: TFD information set by the FH 5016 * @seq_ctl: sequence control from the Tx cmd 5017 * @byte_cnt: byte count from the Tx cmd 5018 * @tlc_info: TLC rate info 5019 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 5020 * @frame_ctrl: frame control 5021 * @status: for non-agg: frame status IWM_TX_STATUS_* 5022 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 5023 * follow this one, up to frame_count. 5024 * 5025 * After the array of statuses comes the SSN of the SCD. Look at 5026 * %iwm_get_scd_ssn for more details. 5027 */ 5028 struct iwm_tx_resp { 5029 uint8_t frame_count; 5030 uint8_t bt_kill_count; 5031 uint8_t failure_rts; 5032 uint8_t failure_frame; 5033 uint32_t initial_rate; 5034 uint16_t wireless_media_time; 5035 5036 uint8_t pa_status; 5037 uint8_t pa_integ_res_a[3]; 5038 uint8_t pa_integ_res_b[3]; 5039 uint8_t pa_integ_res_c[3]; 5040 uint16_t measurement_req_id; 5041 uint16_t reserved; 5042 5043 uint32_t tfd_info; 5044 uint16_t seq_ctl; 5045 uint16_t byte_cnt; 5046 uint8_t tlc_info; 5047 uint8_t ra_tid; 5048 uint16_t frame_ctrl; 5049 5050 struct iwm_agg_tx_status status; 5051 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 5052 5053 /** 5054 * struct iwm_ba_notif - notifies about reception of BA 5055 * ( IWM_BA_NOTIF = 0xc5 ) 5056 * @sta_addr_lo32: lower 32 bits of the MAC address 5057 * @sta_addr_hi16: upper 16 bits of the MAC address 5058 * @sta_id: Index of recipient (BA-sending) station in fw's station table 5059 * @tid: tid of the session 5060 * @seq_ctl: 5061 * @bitmap: the bitmap of the BA notification as seen in the air 5062 * @scd_flow: the tx queue this BA relates to 5063 * @scd_ssn: the index of the last contiguously sent packet 5064 * @txed: number of Txed frames in this batch 5065 * @txed_2_done: number of Acked frames in this batch 5066 */ 5067 struct iwm_ba_notif { 5068 uint32_t sta_addr_lo32; 5069 uint16_t sta_addr_hi16; 5070 uint16_t reserved; 5071 5072 uint8_t sta_id; 5073 uint8_t tid; 5074 uint16_t seq_ctl; 5075 uint64_t bitmap; 5076 uint16_t scd_flow; 5077 uint16_t scd_ssn; 5078 uint8_t txed; 5079 uint8_t txed_2_done; 5080 uint8_t reduced_txp; 5081 uint8_t reserved1; 5082 } __packed; 5083 5084 /* 5085 * struct iwm_mac_beacon_cmd - beacon template command 5086 * @tx: the tx commands associated with the beacon frame 5087 * @template_id: currently equal to the mac context id of the corresponding 5088 * mac. 5089 * @tim_idx: the offset of the tim IE in the beacon 5090 * @tim_size: the length of the tim IE 5091 * @frame: the template of the beacon frame 5092 */ 5093 struct iwm_mac_beacon_cmd { 5094 struct iwm_tx_cmd tx; 5095 uint32_t template_id; 5096 uint32_t tim_idx; 5097 uint32_t tim_size; 5098 struct ieee80211_frame frame[0]; 5099 } __packed; 5100 5101 struct iwm_beacon_notif { 5102 struct iwm_tx_resp beacon_notify_hdr; 5103 uint64_t tsf; 5104 uint32_t ibss_mgr_status; 5105 } __packed; 5106 5107 /** 5108 * enum iwm_dump_control - dump (flush) control flags 5109 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 5110 * and the TFD queues are empty. 5111 */ 5112 enum iwm_dump_control { 5113 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 5114 }; 5115 5116 /** 5117 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 5118 * @queues_ctl: bitmap of queues to flush 5119 * @flush_ctl: control flags 5120 * @reserved: reserved 5121 */ 5122 struct iwm_tx_path_flush_cmd_v1 { 5123 uint32_t queues_ctl; 5124 uint16_t flush_ctl; 5125 uint16_t reserved; 5126 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 5127 5128 /** 5129 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command 5130 * @sta_id: station ID to flush 5131 * @tid_mask: TID mask to flush 5132 * @reserved: reserved 5133 */ 5134 struct iwm_tx_path_flush_cmd { 5135 uint32_t sta_id; 5136 uint16_t tid_mask; 5137 uint16_t reserved; 5138 } __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */ 5139 5140 /** 5141 * iwm_get_scd_ssn - returns the SSN of the SCD 5142 * @tx_resp: the Tx response from the fw (agg or non-agg) 5143 * 5144 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 5145 * it can't know that everything will go well until the end of the AMPDU, it 5146 * can't know in advance the number of MPDUs that will be sent in the current 5147 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 5148 * Hence, it can't know in advance what the SSN of the SCD will be at the end 5149 * of the batch. This is why the SSN of the SCD is written at the end of the 5150 * whole struct at a variable offset. This function knows how to cope with the 5151 * variable offset and returns the SSN of the SCD. 5152 */ 5153 static __inline uint32_t iwm_get_scd_ssn(struct iwm_tx_resp *tx_resp) 5154 { 5155 return le32_to_cpup((uint32_t *)&tx_resp->status + 5156 tx_resp->frame_count) & 0xfff; 5157 } 5158 5159 /** 5160 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 5161 * @token: 5162 * @sta_id: station id 5163 * @tid: 5164 * @scd_queue: scheduler queue to confiug 5165 * @enable: 1 queue enable, 0 queue disable 5166 * @aggregate: 1 aggregated queue, 0 otherwise 5167 * @tx_fifo: %enum iwm_tx_fifo 5168 * @window: BA window size 5169 * @ssn: SSN for the BA agreement 5170 */ 5171 struct iwm_scd_txq_cfg_cmd { 5172 uint8_t token; 5173 uint8_t sta_id; 5174 uint8_t tid; 5175 uint8_t scd_queue; 5176 uint8_t enable; 5177 uint8_t aggregate; 5178 uint8_t tx_fifo; 5179 uint8_t window; 5180 uint16_t ssn; 5181 uint16_t reserved; 5182 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 5183 5184 /** 5185 * struct iwm_scd_txq_cfg_rsp 5186 * @token: taken from the command 5187 * @sta_id: station id from the command 5188 * @tid: tid from the command 5189 * @scd_queue: scd_queue from the command 5190 */ 5191 struct iwm_scd_txq_cfg_rsp { 5192 uint8_t token; 5193 uint8_t sta_id; 5194 uint8_t tid; 5195 uint8_t scd_queue; 5196 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 5197 5198 5199 /* Scan Commands, Responses, Notifications */ 5200 5201 /* Masks for iwm_scan_channel.type flags */ 5202 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 5203 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 5204 #define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22) 5205 5206 /* Max number of IEs for direct SSID scans in a command */ 5207 #define IWM_PROBE_OPTION_MAX 20 5208 5209 /** 5210 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table 5211 * @channel: band is selected by iwm_scan_cmd "flags" field 5212 * @tx_gain: gain for analog radio 5213 * @dsp_atten: gain for DSP 5214 * @active_dwell: dwell time for active scan in TU, typically 5-50 5215 * @passive_dwell: dwell time for passive scan in TU, typically 20-500 5216 * @type: type is broken down to these bits: 5217 * bit 0: 0 = passive, 1 = active 5218 * bits 1-20: SSID direct bit map. If any of these bits is set then 5219 * the corresponding SSID IE is transmitted in probe request 5220 * (bit i adds IE in position i to the probe request) 5221 * bit 22: channel width, 0 = regular, 1 = TGj narrow channel 5222 * 5223 * @iteration_count: 5224 * @iteration_interval: 5225 * This struct is used once for each channel in the scan list. 5226 * Each channel can independently select: 5227 * 1) SSID for directed active scans 5228 * 2) Txpower setting (for rate specified within Tx command) 5229 * 3) How long to stay on-channel (behavior may be modified by quiet_time, 5230 * quiet_plcp_th, good_CRC_th) 5231 * 5232 * To avoid uCode errors, make sure the following are true (see comments 5233 * under struct iwm_scan_cmd about max_out_time and quiet_time): 5234 * 1) If using passive_dwell (i.e. passive_dwell != 0): 5235 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0) 5236 * 2) quiet_time <= active_dwell 5237 * 3) If restricting off-channel time (i.e. max_out_time !=0): 5238 * passive_dwell < max_out_time 5239 * active_dwell < max_out_time 5240 */ 5241 struct iwm_scan_channel { 5242 uint32_t type; 5243 uint16_t channel; 5244 uint16_t iteration_count; 5245 uint32_t iteration_interval; 5246 uint16_t active_dwell; 5247 uint16_t passive_dwell; 5248 } __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */ 5249 5250 /** 5251 * struct iwm_ssid_ie - directed scan network information element 5252 * 5253 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 5254 * selected by "type" bit field in struct iwm_scan_channel; 5255 * each channel may select different ssids from among the 20 entries. 5256 * SSID IEs get transmitted in reverse order of entry. 5257 */ 5258 struct iwm_ssid_ie { 5259 uint8_t id; 5260 uint8_t len; 5261 uint8_t ssid[IEEE80211_NWID_LEN]; 5262 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5263 5264 #define IWM_DEFAULT_SCAN_CHANNELS 40 5265 #define IWM_MAX_SCAN_CHANNELS 52 /* as of 8265-34 firmware image */ 5266 5267 /* scan offload */ 5268 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 5269 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 5270 #define IWM_SCAN_MAX_PROFILES 11 5271 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 5272 5273 /* Default watchdog (in MS) for scheduled scan iteration */ 5274 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 5275 5276 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 5277 #define IWM_CAN_ABORT_STATUS 1 5278 5279 #define IWM_FULL_SCAN_MULTIPLIER 5 5280 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 5281 #define IWM_MAX_SCHED_SCAN_PLANS 2 5282 5283 /** 5284 * iwm_scan_flags - masks for scan command flags 5285 *@IWM_SCAN_FLAGS_PERIODIC_SCAN: 5286 *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX: 5287 *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND: 5288 *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND: 5289 *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN: 5290 *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active 5291 * in the past hour, even if they are marked as passive. 5292 */ 5293 enum iwm_scan_flags { 5294 IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0), 5295 IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1), 5296 IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2), 5297 IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3), 5298 IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4), 5299 IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5), 5300 }; 5301 5302 /** 5303 * enum iwm_scan_type - Scan types for scan command 5304 * @IWM_SCAN_TYPE_FORCED: 5305 * @IWM_SCAN_TYPE_BACKGROUND: 5306 * @IWM_SCAN_TYPE_OS: 5307 * @IWM_SCAN_TYPE_ROAMING: 5308 * @IWM_SCAN_TYPE_ACTION: 5309 * @IWM_SCAN_TYPE_DISCOVERY: 5310 * @IWM_SCAN_TYPE_DISCOVERY_FORCED: 5311 */ 5312 enum iwm_scan_type { 5313 IWM_SCAN_TYPE_FORCED = 0, 5314 IWM_SCAN_TYPE_BACKGROUND = 1, 5315 IWM_SCAN_TYPE_OS = 2, 5316 IWM_SCAN_TYPE_ROAMING = 3, 5317 IWM_SCAN_TYPE_ACTION = 4, 5318 IWM_SCAN_TYPE_DISCOVERY = 5, 5319 IWM_SCAN_TYPE_DISCOVERY_FORCED = 6, 5320 }; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */ 5321 5322 /* Maximal number of channels to scan */ 5323 #define IWM_MAX_NUM_SCAN_CHANNELS 0x24 5324 5325 /** 5326 * iwm_scan_schedule_lmac - schedule of scan offload 5327 * @delay: delay between iterations, in seconds. 5328 * @iterations: num of scan iterations 5329 * @full_scan_mul: number of partial scans before each full scan 5330 */ 5331 struct iwm_scan_schedule_lmac { 5332 uint16_t delay; 5333 uint8_t iterations; 5334 uint8_t full_scan_mul; 5335 } __packed; /* SCAN_SCHEDULE_API_S */ 5336 5337 /** 5338 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 5339 * @tx_flags: combination of TX_CMD_FLG_* 5340 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5341 * cleared. Combination of RATE_MCS_* 5342 * @sta_id: index of destination station in FW station table 5343 * @reserved: for alignment and future use 5344 */ 5345 struct iwm_scan_req_tx_cmd { 5346 uint32_t tx_flags; 5347 uint32_t rate_n_flags; 5348 uint8_t sta_id; 5349 uint8_t reserved[3]; 5350 } __packed; 5351 5352 enum iwm_scan_channel_flags_lmac { 5353 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 5354 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 5355 }; 5356 5357 /** 5358 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 5359 * @flags: bits 1-20: directed scan to i'th ssid 5360 * other bits &enum iwm_scan_channel_flags_lmac 5361 * @channel_number: channel number 1-13 etc 5362 * @iter_count: scan iteration on this channel 5363 * @iter_interval: interval in seconds between iterations on one channel 5364 */ 5365 struct iwm_scan_channel_cfg_lmac { 5366 uint32_t flags; 5367 uint16_t channel_num; 5368 uint16_t iter_count; 5369 uint32_t iter_interval; 5370 } __packed; 5371 5372 /* 5373 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 5374 * @offset: offset in the data block 5375 * @len: length of the segment 5376 */ 5377 struct iwm_scan_probe_segment { 5378 uint16_t offset; 5379 uint16_t len; 5380 } __packed; 5381 5382 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 5383 * @mac_header: first (and common) part of the probe 5384 * @band_data: band specific data 5385 * @common_data: last (and common) part of the probe 5386 * @buf: raw data block 5387 */ 5388 struct iwm_scan_probe_req_v1 { 5389 struct iwm_scan_probe_segment mac_header; 5390 struct iwm_scan_probe_segment band_data[2]; 5391 struct iwm_scan_probe_segment common_data; 5392 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5393 } __packed; 5394 5395 /* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2 5396 * @mac_header: first (and common) part of the probe 5397 * @band_data: band specific data 5398 * @common_data: last (and common) part of the probe 5399 * @buf: raw data block 5400 */ 5401 struct iwm_scan_probe_req { 5402 struct iwm_scan_probe_segment mac_header; 5403 struct iwm_scan_probe_segment band_data[3]; 5404 struct iwm_scan_probe_segment common_data; 5405 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5406 } __packed; 5407 5408 enum iwm_scan_channel_flags { 5409 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 5410 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 5411 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 5412 }; 5413 5414 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 5415 * @flags: enum iwm_scan_channel_flags 5416 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 5417 * involved. 5418 * 1 - EBS is disabled. 5419 * 2 - every second scan will be full scan(and so on). 5420 */ 5421 struct iwm_scan_channel_opt { 5422 uint16_t flags; 5423 uint16_t non_ebs_ratio; 5424 } __packed; 5425 5426 /** 5427 * iwm_mvm_lmac_scan_flags - LMAC scan flags 5428 * @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 5429 * without filtering. 5430 * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 5431 * @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 5432 * @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 5433 * @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 5434 * @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 5435 * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 5436 * and DS parameter set IEs into probe requests. 5437 * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 5438 * 1, 6 and 11. 5439 * @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 5440 */ 5441 enum iwm_mvm_lmac_scan_flags { 5442 IWM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 5443 IWM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 5444 IWM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 5445 IWM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 5446 IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 5447 IWM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 5448 IWM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 5449 IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 5450 IWM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 5451 }; 5452 5453 enum iwm_scan_priority { 5454 IWM_SCAN_PRIORITY_LOW, 5455 IWM_SCAN_PRIORITY_MEDIUM, 5456 IWM_SCAN_PRIORITY_HIGH, 5457 }; 5458 5459 /** 5460 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 5461 * @reserved1: for alignment and future use 5462 * @channel_num: num of channels to scan 5463 * @active-dwell: dwell time for active channels 5464 * @passive-dwell: dwell time for passive channels 5465 * @fragmented-dwell: dwell time for fragmented passive scan 5466 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 5467 * @reserved2: for alignment and future use 5468 * @rx_chain_select: PHY_RX_CHAIN_* flags 5469 * @scan_flags: &enum iwm_lmac_scan_flags 5470 * @max_out_time: max time (in TU) to be out of associated channel 5471 * @suspend_time: pause scan this long (TUs) when returning to service channel 5472 * @flags: RXON flags 5473 * @filter_flags: RXON filter 5474 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 5475 * @direct_scan: list of SSIDs for directed active scan 5476 * @scan_prio: enum iwm_scan_priority 5477 * @iter_num: number of scan iterations 5478 * @delay: delay in seconds before first iteration 5479 * @schedule: two scheduling plans. The first one is finite, the second one can 5480 * be infinite. 5481 * @channel_opt: channel optimization options, for full and partial scan 5482 * @data: channel configuration and probe request packet. 5483 */ 5484 struct iwm_scan_req_lmac { 5485 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 5486 uint32_t reserved1; 5487 uint8_t n_channels; 5488 uint8_t active_dwell; 5489 uint8_t passive_dwell; 5490 uint8_t fragmented_dwell; 5491 uint8_t extended_dwell; 5492 uint8_t reserved2; 5493 uint16_t rx_chain_select; 5494 uint32_t scan_flags; 5495 uint32_t max_out_time; 5496 uint32_t suspend_time; 5497 /* RX_ON_FLAGS_API_S_VER_1 */ 5498 uint32_t flags; 5499 uint32_t filter_flags; 5500 struct iwm_scan_req_tx_cmd tx_cmd[2]; 5501 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5502 uint32_t scan_prio; 5503 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 5504 uint32_t iter_num; 5505 uint32_t delay; 5506 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5507 struct iwm_scan_channel_opt channel_opt[2]; 5508 uint8_t data[]; 5509 } __packed; 5510 5511 /** 5512 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 5513 * @last_schedule_line: last schedule line executed (fast or regular) 5514 * @last_schedule_iteration: last scan iteration executed before scan abort 5515 * @status: enum iwm_scan_offload_complete_status 5516 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 5517 * @time_after_last_iter; time in seconds elapsed after last iteration 5518 */ 5519 struct iwm_periodic_scan_complete { 5520 uint8_t last_schedule_line; 5521 uint8_t last_schedule_iteration; 5522 uint8_t status; 5523 uint8_t ebs_status; 5524 uint32_t time_after_last_iter; 5525 uint32_t reserved; 5526 } __packed; 5527 5528 /* Response to scan request contains only status with one of these values */ 5529 #define IWM_SCAN_RESPONSE_OK 0x1 5530 #define IWM_SCAN_RESPONSE_ERROR 0x2 5531 5532 /* 5533 * IWM_SCAN_ABORT_CMD = 0x81 5534 * When scan abort is requested, the command has no fields except the common 5535 * header. The response contains only a status with one of these values. 5536 */ 5537 #define IWM_SCAN_ABORT_POSSIBLE 0x1 5538 #define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */ 5539 5540 /* TODO: complete documentation */ 5541 #define IWM_SCAN_OWNER_STATUS 0x1 5542 #define IWM_MEASURE_OWNER_STATUS 0x2 5543 5544 /** 5545 * struct iwm_scan_start_notif - notifies start of scan in the device 5546 * ( IWM_SCAN_START_NOTIFICATION = 0x82 ) 5547 * @tsf_low: TSF timer (lower half) in usecs 5548 * @tsf_high: TSF timer (higher half) in usecs 5549 * @beacon_timer: structured as follows: 5550 * bits 0:19 - beacon interval in usecs 5551 * bits 20:23 - reserved (0) 5552 * bits 24:31 - number of beacons 5553 * @channel: which channel is scanned 5554 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5555 * @status: one of *_OWNER_STATUS 5556 */ 5557 struct iwm_scan_start_notif { 5558 uint32_t tsf_low; 5559 uint32_t tsf_high; 5560 uint32_t beacon_timer; 5561 uint8_t channel; 5562 uint8_t band; 5563 uint8_t reserved[2]; 5564 uint32_t status; 5565 } __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */ 5566 5567 /* scan results probe_status first bit indicates success */ 5568 #define IWM_SCAN_PROBE_STATUS_OK 0 5569 #define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0) 5570 /* error statuses combined with TX_FAILED */ 5571 #define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1) 5572 #define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2) 5573 5574 /* How many statistics are gathered for each channel */ 5575 #define IWM_SCAN_RESULTS_STATISTICS 1 5576 5577 /** 5578 * enum iwm_scan_complete_status - status codes for scan complete notifications 5579 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 5580 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 5581 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 5582 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 5583 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 5584 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 5585 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 5586 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 5587 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 5588 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 5589 * (not an error!) 5590 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 5591 * asked for 5592 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 5593 */ 5594 enum iwm_scan_complete_status { 5595 IWM_SCAN_COMP_STATUS_OK = 0x1, 5596 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 5597 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 5598 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 5599 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 5600 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 5601 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 5602 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 5603 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 5604 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 5605 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 5606 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 5607 }; 5608 5609 /** 5610 * struct iwm_scan_results_notif - scan results for one channel 5611 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 5612 * @channel: which channel the results are from 5613 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5614 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5615 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5616 * @duration: duration spent in channel, in usecs 5617 * @statistics: statistics gathered for this channel 5618 */ 5619 struct iwm_scan_results_notif { 5620 uint8_t channel; 5621 uint8_t band; 5622 uint8_t probe_status; 5623 uint8_t num_probe_not_sent; 5624 uint32_t duration; 5625 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5626 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5627 5628 /** 5629 * struct iwm_scan_complete_notif - notifies end of scanning (all channels) 5630 * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 ) 5631 * @scanned_channels: number of channels scanned (and number of valid results) 5632 * @status: one of IWM_SCAN_COMP_STATUS_* 5633 * @bt_status: BT on/off status 5634 * @last_channel: last channel that was scanned 5635 * @tsf_low: TSF timer (lower half) in usecs 5636 * @tsf_high: TSF timer (higher half) in usecs 5637 * @results: all scan results, only "scanned_channels" of them are valid 5638 */ 5639 struct iwm_scan_complete_notif { 5640 uint8_t scanned_channels; 5641 uint8_t status; 5642 uint8_t bt_status; 5643 uint8_t last_channel; 5644 uint32_t tsf_low; 5645 uint32_t tsf_high; 5646 struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS]; 5647 } __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */ 5648 5649 enum iwm_scan_framework_client { 5650 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5651 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5652 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5653 }; 5654 5655 /** 5656 * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6 5657 * @scan_flags: see enum iwm_scan_flags 5658 * @channel_count: channels in channel list 5659 * @quiet_time: dwell time, in milisiconds, on quiet channel 5660 * @quiet_plcp_th: quiet channel num of packets threshold 5661 * @good_CRC_th: passive to active promotion threshold 5662 * @rx_chain: RXON rx chain. 5663 * @max_out_time: max uSec to be out of assoceated channel 5664 * @suspend_time: pause scan this long when returning to service channel 5665 * @flags: RXON flags 5666 * @filter_flags: RXONfilter 5667 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz. 5668 * @direct_scan: list of SSIDs for directed active scan 5669 * @scan_type: see enum iwm_scan_type. 5670 * @rep_count: repetition count for each scheduled scan iteration. 5671 */ 5672 struct iwm_scan_offload_cmd { 5673 uint16_t len; 5674 uint8_t scan_flags; 5675 uint8_t channel_count; 5676 uint16_t quiet_time; 5677 uint16_t quiet_plcp_th; 5678 uint16_t good_CRC_th; 5679 uint16_t rx_chain; 5680 uint32_t max_out_time; 5681 uint32_t suspend_time; 5682 /* IWM_RX_ON_FLAGS_API_S_VER_1 */ 5683 uint32_t flags; 5684 uint32_t filter_flags; 5685 struct iwm_tx_cmd tx_cmd[2]; 5686 /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5687 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5688 uint32_t scan_type; 5689 uint32_t rep_count; 5690 } __packed; 5691 5692 enum iwm_scan_offload_channel_flags { 5693 IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0), 5694 IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22), 5695 IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24), 5696 IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25), 5697 }; 5698 5699 /** 5700 * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S 5701 * @type: bitmap - see enum iwm_scan_offload_channel_flags. 5702 * 0: passive (0) or active (1) scan. 5703 * 1-20: directed scan to i'th ssid. 5704 * 22: channel width configuration - 1 for narrow. 5705 * 24: full scan. 5706 * 25: partial scan. 5707 * @channel_number: channel number 1-13 etc. 5708 * @iter_count: repetition count for the channel. 5709 * @iter_interval: interval between two iterations on one channel. 5710 * @dwell_time: entry 0 - active scan, entry 1 - passive scan. 5711 */ 5712 struct iwm_scan_channel_cfg { 5713 uint32_t type[IWM_MAX_SCAN_CHANNELS]; 5714 uint16_t channel_number[IWM_MAX_SCAN_CHANNELS]; 5715 uint16_t iter_count[IWM_MAX_SCAN_CHANNELS]; 5716 uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS]; 5717 uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2]; 5718 } __packed; 5719 5720 /** 5721 * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S 5722 * @scan_cmd: scan command fixed part 5723 * @channel_cfg: scan channel configuration 5724 * @data: probe request frames (one per band) 5725 */ 5726 struct iwm_scan_offload_cfg { 5727 struct iwm_scan_offload_cmd scan_cmd; 5728 struct iwm_scan_channel_cfg channel_cfg; 5729 uint8_t data[0]; 5730 } __packed; 5731 5732 /** 5733 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5734 * @ssid: MAC address to filter out 5735 * @reported_rssi: AP rssi reported to the host 5736 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5737 */ 5738 struct iwm_scan_offload_blacklist { 5739 uint8_t ssid[ETHER_ADDR_LEN]; 5740 uint8_t reported_rssi; 5741 uint8_t client_bitmap; 5742 } __packed; 5743 5744 enum iwm_scan_offload_network_type { 5745 IWM_NETWORK_TYPE_BSS = 1, 5746 IWM_NETWORK_TYPE_IBSS = 2, 5747 IWM_NETWORK_TYPE_ANY = 3, 5748 }; 5749 5750 enum iwm_scan_offload_band_selection { 5751 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5752 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5753 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5754 }; 5755 5756 /** 5757 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5758 * @ssid_index: index to ssid list in fixed part 5759 * @unicast_cipher: encryption olgorithm to match - bitmap 5760 * @aut_alg: authentication olgorithm to match - bitmap 5761 * @network_type: enum iwm_scan_offload_network_type 5762 * @band_selection: enum iwm_scan_offload_band_selection 5763 * @client_bitmap: clients waiting for match - enum scan_framework_client 5764 */ 5765 struct iwm_scan_offload_profile { 5766 uint8_t ssid_index; 5767 uint8_t unicast_cipher; 5768 uint8_t auth_alg; 5769 uint8_t network_type; 5770 uint8_t band_selection; 5771 uint8_t client_bitmap; 5772 uint8_t reserved[2]; 5773 } __packed; 5774 5775 /** 5776 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5777 * @blaclist: AP list to filter off from scan results 5778 * @profiles: profiles to search for match 5779 * @blacklist_len: length of blacklist 5780 * @num_profiles: num of profiles in the list 5781 * @match_notify: clients waiting for match found notification 5782 * @pass_match: clients waiting for the results 5783 * @active_clients: active clients bitmap - enum scan_framework_client 5784 * @any_beacon_notify: clients waiting for match notification without match 5785 */ 5786 struct iwm_scan_offload_profile_cfg { 5787 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5788 uint8_t blacklist_len; 5789 uint8_t num_profiles; 5790 uint8_t match_notify; 5791 uint8_t pass_match; 5792 uint8_t active_clients; 5793 uint8_t any_beacon_notify; 5794 uint8_t reserved[2]; 5795 } __packed; 5796 5797 /** 5798 * iwm_scan_offload_schedule - schedule of scan offload 5799 * @delay: delay between iterations, in seconds. 5800 * @iterations: num of scan iterations 5801 * @full_scan_mul: number of partial scans before each full scan 5802 */ 5803 struct iwm_scan_offload_schedule { 5804 uint16_t delay; 5805 uint8_t iterations; 5806 uint8_t full_scan_mul; 5807 } __packed; 5808 5809 /* 5810 * iwm_scan_offload_flags 5811 * 5812 * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering. 5813 * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan. 5814 * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan 5815 * on A band. 5816 */ 5817 enum iwm_scan_offload_flags { 5818 IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0), 5819 IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2), 5820 IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3), 5821 }; 5822 5823 /** 5824 * iwm_scan_offload_req - scan offload request command 5825 * @flags: bitmap - enum iwm_scan_offload_flags. 5826 * @watchdog: maximum scan duration in TU. 5827 * @delay: delay in seconds before first iteration. 5828 * @schedule_line: scan offload schedule, for fast and regular scan. 5829 */ 5830 struct iwm_scan_offload_req { 5831 uint16_t flags; 5832 uint16_t watchdog; 5833 uint16_t delay; 5834 uint16_t reserved; 5835 struct iwm_scan_offload_schedule schedule_line[2]; 5836 } __packed; 5837 5838 enum iwm_scan_offload_compleate_status { 5839 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5840 IWM_SCAN_OFFLOAD_ABORTED = 2, 5841 }; 5842 5843 /** 5844 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5845 * SCAN_COMPLETE_NTF_API_S_VER_3 5846 * @scanned_channels: number of channels scanned (and number of valid results) 5847 * @status: one of SCAN_COMP_STATUS_* 5848 * @bt_status: BT on/off status 5849 * @last_channel: last channel that was scanned 5850 * @tsf_low: TSF timer (lower half) in usecs 5851 * @tsf_high: TSF timer (higher half) in usecs 5852 * @results: an array of scan results, only "scanned_channels" of them are valid 5853 */ 5854 struct iwm_lmac_scan_complete_notif { 5855 uint8_t scanned_channels; 5856 uint8_t status; 5857 uint8_t bt_status; 5858 uint8_t last_channel; 5859 uint32_t tsf_low; 5860 uint32_t tsf_high; 5861 struct iwm_scan_results_notif results[]; 5862 } __packed; 5863 5864 5865 /** 5866 * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1 5867 * @last_schedule_line: last schedule line executed (fast or regular) 5868 * @last_schedule_iteration: last scan iteration executed before scan abort 5869 * @status: enum iwm_scan_offload_compleate_status 5870 */ 5871 struct iwm_scan_offload_complete { 5872 uint8_t last_schedule_line; 5873 uint8_t last_schedule_iteration; 5874 uint8_t status; 5875 uint8_t reserved; 5876 } __packed; 5877 5878 /** 5879 * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1 5880 * @ssid_bitmap: SSIDs indexes found in this iteration 5881 * @client_bitmap: clients that are active and wait for this notification 5882 */ 5883 struct iwm_sched_scan_results { 5884 uint16_t ssid_bitmap; 5885 uint8_t client_bitmap; 5886 uint8_t reserved; 5887 }; 5888 5889 /* UMAC Scan API */ 5890 5891 /* The maximum of either of these cannot exceed 8, because we use an 5892 * 8-bit mask (see IWM_SCAN_MASK). 5893 */ 5894 #define IWM_MAX_UMAC_SCANS 8 5895 #define IWM_MAX_LMAC_SCANS 1 5896 5897 enum iwm_scan_config_flags { 5898 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5899 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5900 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5901 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5902 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5903 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5904 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5905 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5906 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5907 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5908 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5909 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5910 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5911 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5912 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5913 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5914 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5915 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5916 5917 /* Bits 26-31 are for num of channels in channel_array */ 5918 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5919 }; 5920 5921 enum iwm_scan_config_rates { 5922 /* OFDM basic rates */ 5923 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5924 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5925 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5926 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5927 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5928 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5929 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5930 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5931 /* CCK basic rates */ 5932 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5933 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5934 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5935 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5936 5937 /* Bits 16-27 are for supported rates */ 5938 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5939 }; 5940 5941 enum iwm_channel_flags { 5942 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5943 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5944 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5945 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5946 }; 5947 5948 /** 5949 * struct iwm_scan_config 5950 * @flags: enum scan_config_flags 5951 * @tx_chains: valid_tx antenna - ANT_* definitions 5952 * @rx_chains: valid_rx antenna - ANT_* definitions 5953 * @legacy_rates: default legacy rates - enum scan_config_rates 5954 * @out_of_channel_time: default max out of serving channel time 5955 * @suspend_time: default max suspend time 5956 * @dwell_active: default dwell time for active scan 5957 * @dwell_passive: default dwell time for passive scan 5958 * @dwell_fragmented: default dwell time for fragmented scan 5959 * @dwell_extended: default dwell time for channels 1, 6 and 11 5960 * @mac_addr: default mac address to be used in probes 5961 * @bcast_sta_id: the index of the station in the fw 5962 * @channel_flags: default channel flags - enum iwm_channel_flags 5963 * scan_config_channel_flag 5964 * @channel_array: default supported channels 5965 */ 5966 struct iwm_scan_config { 5967 uint32_t flags; 5968 uint32_t tx_chains; 5969 uint32_t rx_chains; 5970 uint32_t legacy_rates; 5971 uint32_t out_of_channel_time; 5972 uint32_t suspend_time; 5973 uint8_t dwell_active; 5974 uint8_t dwell_passive; 5975 uint8_t dwell_fragmented; 5976 uint8_t dwell_extended; 5977 uint8_t mac_addr[ETHER_ADDR_LEN]; 5978 uint8_t bcast_sta_id; 5979 uint8_t channel_flags; 5980 uint8_t channel_array[]; 5981 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5982 5983 /** 5984 * iwm_umac_scan_flags 5985 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5986 * can be preempted by other scan requests with higher priority. 5987 * The low priority scan will be resumed when the higher proirity scan is 5988 * completed. 5989 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5990 * when scan starts. 5991 */ 5992 enum iwm_umac_scan_flags { 5993 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5994 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5995 }; 5996 5997 enum iwm_umac_scan_uid_offsets { 5998 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5999 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 6000 }; 6001 6002 enum iwm_umac_scan_general_flags { 6003 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 6004 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 6005 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 6006 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 6007 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 6008 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 6009 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 6010 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 6011 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 6012 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 6013 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 6014 /* Extended dwell is obsolete when adaptive dwell is used, making this 6015 * bit reusable. Hence, probe request defer is used only when adaptive 6016 * dwell is supported. */ 6017 IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP = (1 << 10), 6018 IWM_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED = (1 << 11), 6019 IWM_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL = (1 << 13), 6020 IWM_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME = (1 << 14), 6021 IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE = (1 << 15), 6022 }; 6023 6024 /** 6025 * UMAC scan general flags #2 6026 * @IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete 6027 * notification per channel or not. 6028 * @IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel 6029 * reorder optimization or not. 6030 */ 6031 enum iwm_umac_scan_general_flags2 { 6032 IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL = (1 << 0), 6033 IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER = (1 << 1), 6034 }; 6035 6036 /** 6037 * struct iwm_scan_channel_cfg_umac 6038 * @flags: bitmap - 0-19: directed scan to i'th ssid. 6039 * @channel_num: channel number 1-13 etc. 6040 * @iter_count: repetition count for the channel. 6041 * @iter_interval: interval between two scan iterations on one channel. 6042 */ 6043 struct iwm_scan_channel_cfg_umac { 6044 uint32_t flags; 6045 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 6046 uint8_t channel_num; 6047 uint8_t iter_count; 6048 uint16_t iter_interval; 6049 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 6050 6051 /** 6052 * struct iwm_scan_umac_schedule 6053 * @interval: interval in seconds between scan iterations 6054 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 6055 * @reserved: for alignment and future use 6056 */ 6057 struct iwm_scan_umac_schedule { 6058 uint16_t interval; 6059 uint8_t iter_count; 6060 uint8_t reserved; 6061 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 6062 6063 /** 6064 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 6065 * parameters following channels configuration array. 6066 * @schedule: two scheduling plans. 6067 * @delay: delay in TUs before starting the first scan iteration 6068 * @reserved: for future use and alignment 6069 * @preq: probe request with IEs blocks 6070 * @direct_scan: list of SSIDs for directed active scan 6071 */ 6072 struct iwm_scan_req_umac_tail_v1 { 6073 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 6074 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 6075 uint16_t delay; 6076 uint16_t reserved; 6077 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 6078 struct iwm_scan_probe_req_v1 preq; 6079 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 6080 } __packed; 6081 6082 /** 6083 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 6084 * parameters following channels configuration array. 6085 * @schedule: two scheduling plans. 6086 * @delay: delay in TUs before starting the first scan iteration 6087 * @reserved: for future use and alignment 6088 * @preq: probe request with IEs blocks 6089 * @direct_scan: list of SSIDs for directed active scan 6090 */ 6091 struct iwm_scan_req_umac_tail_v2 { 6092 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 6093 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 6094 uint16_t delay; 6095 uint16_t reserved; 6096 /* SCAN_PROBE_PARAMS_API_S_VER_2 */ 6097 struct iwm_scan_probe_req preq; 6098 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 6099 } __packed; 6100 6101 /** 6102 * struct iwm_scan_umac_chan_param 6103 * @flags: channel flags &enum iwl_scan_channel_flags 6104 * @count: num of channels in scan request 6105 * @reserved: for future use and alignment 6106 */ 6107 struct iwm_scan_umac_chan_param { 6108 uint8_t flags; 6109 uint8_t count; 6110 uint16_t reserved; 6111 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 6112 6113 #define IWM_SCAN_LB_LMAC_IDX 0 6114 #define IWM_SCAN_HB_LMAC_IDX 1 6115 6116 /** 6117 * struct iwm_scan_req_umac 6118 * @flags: &enum iwl_umac_scan_flags 6119 * @uid: scan id, &enum iwl_umac_scan_uid_offsets 6120 * @ooc_priority: out of channel priority - &enum iwl_scan_priority 6121 * @general_flags: &enum iwl_umac_scan_general_flags 6122 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF 6123 * @extended_dwell: dwell time for channels 1, 6 and 11 6124 * @active_dwell: dwell time for active scan per LMAC 6125 * @passive_dwell: dwell time for passive scan per LMAC 6126 * @fragmented_dwell: dwell time for fragmented passive scan 6127 * @adwell_default_n_aps: for adaptive dwell the default number of APs 6128 * per channel 6129 * @adwell_default_n_aps_social: for adaptive dwell the default 6130 * number of APs per social (1,6,11) channel 6131 * @general_flags2: &enum iwl_umac_scan_general_flags2 6132 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added 6133 * to total scan time 6134 * @max_out_time: max out of serving channel time, per LMAC - for CDB there 6135 * are 2 LMACs (high band and low band) 6136 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs 6137 * @scan_priority: scan internal prioritization &enum iwl_scan_priority 6138 * @num_of_fragments: Number of fragments needed for full coverage per band. 6139 * Relevant only for fragmented scan. 6140 * @channel: &struct iwm_scan_umac_chan_param 6141 * @reserved: for future use and alignment 6142 * @reserved3: for future use and alignment 6143 * @data: &struct iwm_scan_channel_cfg_umac and 6144 * &struct iwm_scan_req_umac_tail 6145 */ 6146 struct iwm_scan_req_umac { 6147 uint32_t flags; 6148 uint32_t uid; 6149 uint32_t ooc_priority; 6150 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 6151 uint16_t general_flags; 6152 uint8_t reserved; 6153 uint8_t scan_start_mac_id; 6154 union { 6155 struct { 6156 uint8_t extended_dwell; 6157 uint8_t active_dwell; 6158 uint8_t passive_dwell; 6159 uint8_t fragmented_dwell; 6160 uint32_t max_out_time; 6161 uint32_t suspend_time; 6162 uint32_t scan_priority; 6163 struct iwm_scan_umac_chan_param channel; 6164 uint8_t data[]; 6165 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 6166 struct { 6167 uint8_t extended_dwell; 6168 uint8_t active_dwell; 6169 uint8_t passive_dwell; 6170 uint8_t fragmented_dwell; 6171 uint32_t max_out_time[2]; 6172 uint32_t suspend_time[2]; 6173 uint32_t scan_priority; 6174 struct iwm_scan_umac_chan_param channel; 6175 uint8_t data[]; 6176 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */ 6177 struct { 6178 uint8_t active_dwell; 6179 uint8_t passive_dwell; 6180 uint8_t fragmented_dwell; 6181 uint8_t adwell_default_n_aps; 6182 uint8_t adwell_default_n_aps_social; 6183 uint8_t reserved3; 6184 uint16_t adwell_max_budget; 6185 uint32_t max_out_time[2]; 6186 uint32_t suspend_time[2]; 6187 uint32_t scan_priority; 6188 struct iwm_scan_umac_chan_param channel; 6189 uint8_t data[]; 6190 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */ 6191 struct { 6192 uint8_t active_dwell[2]; 6193 uint8_t reserved2; 6194 uint8_t adwell_default_n_aps; 6195 uint8_t adwell_default_n_aps_social; 6196 uint8_t general_flags2; 6197 uint16_t adwell_max_budget; 6198 uint32_t max_out_time[2]; 6199 uint32_t suspend_time[2]; 6200 uint32_t scan_priority; 6201 uint8_t passive_dwell[2]; 6202 uint8_t num_of_fragments[2]; 6203 struct iwm_scan_umac_chan_param channel; 6204 uint8_t data[]; 6205 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */ 6206 struct { 6207 uint8_t active_dwell[2]; 6208 uint8_t adwell_default_hb_n_aps; 6209 uint8_t adwell_default_lb_n_aps; 6210 uint8_t adwell_default_n_aps_social; 6211 uint8_t general_flags2; 6212 uint16_t adwell_max_budget; 6213 uint32_t max_out_time[2]; 6214 uint32_t suspend_time[2]; 6215 uint32_t scan_priority; 6216 uint8_t passive_dwell[2]; 6217 uint8_t num_of_fragments[2]; 6218 struct iwm_scan_umac_chan_param channel; 6219 uint8_t data[]; 6220 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */ 6221 }; 6222 } __packed; 6223 6224 #define IWM_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwm_scan_req_umac) 6225 #define IWM_SCAN_REQ_UMAC_SIZE_V7 48 6226 #define IWM_SCAN_REQ_UMAC_SIZE_V6 44 6227 #define IWM_SCAN_REQ_UMAC_SIZE_V1 36 6228 6229 /** 6230 * struct iwm_umac_scan_abort 6231 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 6232 * @flags: reserved 6233 */ 6234 struct iwm_umac_scan_abort { 6235 uint32_t uid; 6236 uint32_t flags; 6237 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 6238 6239 /** 6240 * struct iwm_umac_scan_complete 6241 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 6242 * @last_schedule: last scheduling line 6243 * @last_iter: last scan iteration number 6244 * @scan status: &enum iwm_scan_offload_complete_status 6245 * @ebs_status: &enum iwm_scan_ebs_status 6246 * @time_from_last_iter: time elapsed from last iteration 6247 * @reserved: for future use 6248 */ 6249 struct iwm_umac_scan_complete { 6250 uint32_t uid; 6251 uint8_t last_schedule; 6252 uint8_t last_iter; 6253 uint8_t status; 6254 uint8_t ebs_status; 6255 uint32_t time_from_last_iter; 6256 uint32_t reserved; 6257 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 6258 6259 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 6260 /** 6261 * struct iwm_scan_offload_profile_match - match information 6262 * @bssid: matched bssid 6263 * @channel: channel where the match occurred 6264 * @energy: 6265 * @matching_feature: 6266 * @matching_channels: bitmap of channels that matched, referencing 6267 * the channels passed in tue scan offload request 6268 */ 6269 struct iwm_scan_offload_profile_match { 6270 uint8_t bssid[ETHER_ADDR_LEN]; 6271 uint16_t reserved; 6272 uint8_t channel; 6273 uint8_t energy; 6274 uint8_t matching_feature; 6275 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 6276 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 6277 6278 /** 6279 * struct iwm_scan_offload_profiles_query - match results query response 6280 * @matched_profiles: bitmap of matched profiles, referencing the 6281 * matches passed in the scan offload request 6282 * @last_scan_age: age of the last offloaded scan 6283 * @n_scans_done: number of offloaded scans done 6284 * @gp2_d0u: GP2 when D0U occurred 6285 * @gp2_invoked: GP2 when scan offload was invoked 6286 * @resume_while_scanning: not used 6287 * @self_recovery: obsolete 6288 * @reserved: reserved 6289 * @matches: array of match information, one for each match 6290 */ 6291 struct iwm_scan_offload_profiles_query { 6292 uint32_t matched_profiles; 6293 uint32_t last_scan_age; 6294 uint32_t n_scans_done; 6295 uint32_t gp2_d0u; 6296 uint32_t gp2_invoked; 6297 uint8_t resume_while_scanning; 6298 uint8_t self_recovery; 6299 uint16_t reserved; 6300 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 6301 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 6302 6303 /** 6304 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 6305 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 6306 * @scanned_channels: number of channels scanned and number of valid elements in 6307 * results array 6308 * @status: one of SCAN_COMP_STATUS_* 6309 * @bt_status: BT on/off status 6310 * @last_channel: last channel that was scanned 6311 * @tsf_low: TSF timer (lower half) in usecs 6312 * @tsf_high: TSF timer (higher half) in usecs 6313 * @results: array of scan results, only "scanned_channels" of them are valid 6314 */ 6315 struct iwm_umac_scan_iter_complete_notif { 6316 uint32_t uid; 6317 uint8_t scanned_channels; 6318 uint8_t status; 6319 uint8_t bt_status; 6320 uint8_t last_channel; 6321 uint32_t tsf_low; 6322 uint32_t tsf_high; 6323 struct iwm_scan_results_notif results[]; 6324 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 6325 6326 /* Please keep this enum *SORTED* by hex value. 6327 * Needed for binary search, otherwise a warning will be triggered. 6328 */ 6329 enum iwm_scan_subcmd_ids { 6330 IWM_GSCAN_START_CMD = 0x0, 6331 IWM_GSCAN_STOP_CMD = 0x1, 6332 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 6333 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 6334 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 6335 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 6336 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 6337 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 6338 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 6339 }; 6340 6341 /* STA API */ 6342 6343 /** 6344 * enum iwm_sta_flags - flags for the ADD_STA host command 6345 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 6346 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 6347 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 6348 * @IWM_STA_FLG_PS: set if STA is in Power Save 6349 * @IWM_STA_FLG_INVALID: set if STA is invalid 6350 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 6351 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 6352 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 6353 * @IWM_STA_FLG_PAN: STA is for PAN interface 6354 * @IWM_STA_FLG_CLASS_AUTH: 6355 * @IWM_STA_FLG_CLASS_ASSOC: 6356 * @IWM_STA_FLG_CLASS_MIMO_PROT: 6357 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 6358 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 6359 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 6360 * initialised by driver and can be updated by fw upon reception of 6361 * action frames that can change the channel width. When cleared the fw 6362 * will send all the frames in 20MHz even when FAT channel is requested. 6363 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 6364 * driver and can be updated by fw upon reception of action frames. 6365 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 6366 */ 6367 enum iwm_sta_flags { 6368 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 6369 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 6370 6371 IWM_STA_FLG_DISABLE_TX = (1 << 4), 6372 6373 IWM_STA_FLG_PS = (1 << 8), 6374 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 6375 IWM_STA_FLG_PAN = (1 << 13), 6376 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 6377 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 6378 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 6379 6380 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 6381 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 6382 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 6383 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 6384 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 6385 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 6386 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 6387 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 6388 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 6389 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 6390 6391 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 6392 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 6393 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 6394 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 6395 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 6396 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 6397 6398 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 6399 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 6400 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 6401 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 6402 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 6403 6404 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 6405 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 6406 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 6407 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 6408 }; 6409 6410 /** 6411 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 6412 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 6413 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 6414 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 6415 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 6416 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 6417 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 6418 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 6419 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 6420 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 6421 * station info array (1 - n 1X mode) 6422 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 6423 * @IWM_STA_KEY_NOT_VALID: key is invalid 6424 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 6425 * @IWM_STA_KEY_MULTICAST: set for multical key 6426 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 6427 */ 6428 enum iwm_sta_key_flag { 6429 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 6430 IWM_STA_KEY_FLG_WEP = (1 << 0), 6431 IWM_STA_KEY_FLG_CCM = (2 << 0), 6432 IWM_STA_KEY_FLG_TKIP = (3 << 0), 6433 IWM_STA_KEY_FLG_EXT = (4 << 0), 6434 IWM_STA_KEY_FLG_CMAC = (6 << 0), 6435 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 6436 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 6437 6438 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 6439 IWM_STA_KEY_FLG_KEYID_POS = 8, 6440 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 6441 IWM_STA_KEY_NOT_VALID = (1 << 11), 6442 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 6443 IWM_STA_KEY_MULTICAST = (1 << 14), 6444 IWM_STA_KEY_MFP = (1 << 15), 6445 }; 6446 6447 /** 6448 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 6449 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 6450 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 6451 * @IWM_STA_MODIFY_TX_RATE: unused 6452 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 6453 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 6454 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 6455 * @IWM_STA_MODIFY_PROT_TH: 6456 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 6457 */ 6458 enum iwm_sta_modify_flag { 6459 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 6460 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 6461 IWM_STA_MODIFY_TX_RATE = (1 << 2), 6462 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 6463 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 6464 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 6465 IWM_STA_MODIFY_PROT_TH = (1 << 6), 6466 IWM_STA_MODIFY_QUEUES = (1 << 7), 6467 }; 6468 6469 #define IWM_STA_MODE_MODIFY 1 6470 6471 /** 6472 * enum iwm_sta_sleep_flag - type of sleep of the station 6473 * @IWM_STA_SLEEP_STATE_AWAKE: 6474 * @IWM_STA_SLEEP_STATE_PS_POLL: 6475 * @IWM_STA_SLEEP_STATE_UAPSD: 6476 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 6477 * (last) released frame 6478 */ 6479 enum iwm_sta_sleep_flag { 6480 IWM_STA_SLEEP_STATE_AWAKE = 0, 6481 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 6482 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 6483 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 6484 }; 6485 6486 /* STA ID and color bits definitions */ 6487 #define IWM_STA_ID_SEED (0x0f) 6488 #define IWM_STA_ID_POS (0) 6489 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 6490 6491 #define IWM_STA_COLOR_SEED (0x7) 6492 #define IWM_STA_COLOR_POS (4) 6493 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 6494 6495 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 6496 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 6497 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 6498 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 6499 6500 #define IWM_STA_KEY_MAX_NUM (16) 6501 #define IWM_STA_KEY_IDX_INVALID (0xff) 6502 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 6503 #define IWM_MAX_GLOBAL_KEYS (4) 6504 #define IWM_STA_KEY_LEN_WEP40 (5) 6505 #define IWM_STA_KEY_LEN_WEP104 (13) 6506 6507 /** 6508 * struct iwm_keyinfo - key information 6509 * @key_flags: type %iwm_sta_key_flag 6510 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6511 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6512 * @key_offset: key offset in the fw's key table 6513 * @key: 16-byte unicast decryption key 6514 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 6515 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 6516 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 6517 */ 6518 struct iwm_keyinfo { 6519 uint16_t key_flags; 6520 uint8_t tkip_rx_tsc_byte2; 6521 uint8_t reserved1; 6522 uint16_t tkip_rx_ttak[5]; 6523 uint8_t key_offset; 6524 uint8_t reserved2; 6525 uint8_t key[16]; 6526 uint64_t tx_secur_seq_cnt; 6527 uint64_t hw_tkip_mic_rx_key; 6528 uint64_t hw_tkip_mic_tx_key; 6529 } __packed; 6530 6531 #define IWM_ADD_STA_STATUS_MASK 0xFF 6532 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 6533 #define IWM_ADD_STA_BAID_MASK 0x7F00 6534 #define IWM_ADD_STA_BAID_SHIFT 8 6535 6536 /** 6537 * struct iwm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 6538 * ( REPLY_ADD_STA = 0x18 ) 6539 * @add_modify: 1: modify existing, 0: add new station 6540 * @awake_acs: 6541 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 6542 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 6543 * @mac_id_n_color: the Mac context this station belongs to 6544 * @addr[ETHER_ADDR_LEN]: station's MAC address 6545 * @sta_id: index of station in uCode's station table 6546 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 6547 * alone. 1 - modify, 0 - don't change. 6548 * @station_flags: look at %iwm_sta_flags 6549 * @station_flags_msk: what of %station_flags have changed 6550 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 6551 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 6552 * add_immediate_ba_ssn. 6553 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 6554 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 6555 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 6556 * add_immediate_ba_tid. 6557 * @sleep_tx_count: number of packets to transmit to station even though it is 6558 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 6559 * keeps track of STA sleep state. 6560 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 6561 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 6562 * mac-addr. 6563 * @beamform_flags: beam forming controls 6564 * @tfd_queue_msk: tfd queues used by this station 6565 * 6566 * The device contains an internal table of per-station information, with info 6567 * on security keys, aggregation parameters, and Tx rates for initial Tx 6568 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 6569 * 6570 * ADD_STA sets up the table entry for one station, either creating a new 6571 * entry, or modifying a pre-existing one. 6572 */ 6573 struct iwm_add_sta_cmd_v7 { 6574 uint8_t add_modify; 6575 uint8_t awake_acs; 6576 uint16_t tid_disable_tx; 6577 uint32_t mac_id_n_color; 6578 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6579 uint16_t reserved2; 6580 uint8_t sta_id; 6581 uint8_t modify_mask; 6582 uint16_t reserved3; 6583 uint32_t station_flags; 6584 uint32_t station_flags_msk; 6585 uint8_t add_immediate_ba_tid; 6586 uint8_t remove_immediate_ba_tid; 6587 uint16_t add_immediate_ba_ssn; 6588 uint16_t sleep_tx_count; 6589 uint16_t sleep_state_flags; 6590 uint16_t assoc_id; 6591 uint16_t beamform_flags; 6592 uint32_t tfd_queue_msk; 6593 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 6594 6595 /** 6596 * struct iwm_add_sta_cmd - Add/modify a station in the fw's sta table. 6597 * ( REPLY_ADD_STA = 0x18 ) 6598 * @add_modify: see &enum iwl_sta_mode 6599 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD) 6600 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 6601 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field. 6602 * @mac_id_n_color: the Mac context this station belongs to, 6603 * see &enum iwl_ctxt_id_and_color 6604 * @addr: station's MAC address 6605 * @reserved2: reserved 6606 * @sta_id: index of station in uCode's station table 6607 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave 6608 * alone. 1 - modify, 0 - don't change. 6609 * @reserved3: reserved 6610 * @station_flags: look at &enum iwl_sta_flags 6611 * @station_flags_msk: what of %station_flags have changed, 6612 * also &enum iwl_sta_flags 6613 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 6614 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set 6615 * add_immediate_ba_ssn. 6616 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 6617 * Set %STA_MODIFY_REMOVE_BA_TID to use this field 6618 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 6619 * add_immediate_ba_tid. 6620 * @sleep_tx_count: number of packets to transmit to station even though it is 6621 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 6622 * keeps track of STA sleep state. 6623 * @station_type: type of this station. See &enum iwl_sta_type. 6624 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag. 6625 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 6626 * mac-addr. 6627 * @beamform_flags: beam forming controls 6628 * @tfd_queue_msk: tfd queues used by this station. 6629 * Obsolete for new TX API (9 and above). 6630 * @rx_ba_window: aggregation window size 6631 * @sp_length: the size of the SP in actual number of frames 6632 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver 6633 * enabled ACs. 6634 * 6635 * The device contains an internal table of per-station information, with info 6636 * on security keys, aggregation parameters, and Tx rates for initial Tx 6637 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD). 6638 * 6639 * ADD_STA sets up the table entry for one station, either creating a new 6640 * entry, or modifying a pre-existing one. 6641 */ 6642 struct iwm_add_sta_cmd { 6643 uint8_t add_modify; 6644 uint8_t awake_acs; 6645 uint16_t tid_disable_tx; 6646 uint32_t mac_id_n_color; 6647 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6648 uint16_t reserved2; 6649 uint8_t sta_id; 6650 uint8_t modify_mask; 6651 uint16_t reserved3; 6652 uint32_t station_flags; 6653 uint32_t station_flags_msk; 6654 uint8_t add_immediate_ba_tid; 6655 uint8_t remove_immediate_ba_tid; 6656 uint16_t add_immediate_ba_ssn; 6657 uint16_t sleep_tx_count; 6658 uint8_t sleep_state_flags; 6659 uint8_t station_type; 6660 uint16_t assoc_id; 6661 uint16_t beamform_flags; 6662 uint32_t tfd_queue_msk; 6663 uint16_t rx_ba_window; 6664 uint8_t sp_length; 6665 uint8_t uapsd_acs; 6666 } __packed; /* ADD_STA_CMD_API_S_VER_10 */ 6667 6668 /** 6669 * FW station types 6670 * ( REPLY_ADD_STA = 0x18 ) 6671 * @IWM_STA_LINK: Link station - normal RX and TX traffic. 6672 * @IWM_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons 6673 * and probe responses. 6674 * @IWM_STA_MULTICAST: multicast traffic, 6675 * @IWM_STA_TDLS_LINK: TDLS link station 6676 * @IWM_STA_AUX_ACTIVITY: auxiliary station (scan, ROC and so on). 6677 */ 6678 enum { 6679 IWM_STA_LINK, 6680 IWM_STA_GENERAL_PURPOSE, 6681 IWM_STA_MULTICAST, 6682 IWM_STA_TDLS_LINK, 6683 IWM_STA_AUX_ACTIVITY, 6684 }; 6685 6686 /** 6687 * struct iwm_add_sta_key_common - add/modify sta key common part 6688 * ( REPLY_ADD_STA_KEY = 0x17 ) 6689 * @sta_id: index of station in uCode's station table 6690 * @key_offset: key offset in key storage 6691 * @key_flags: IWM_STA_KEY_FLG_* 6692 * @key: key material data 6693 * @rx_secur_seq_cnt: RX security sequence counter for the key 6694 */ 6695 struct iwm_add_sta_key_common { 6696 uint8_t sta_id; 6697 uint8_t key_offset; 6698 uint16_t key_flags; 6699 uint8_t key[32]; 6700 uint8_t rx_secur_seq_cnt[16]; 6701 } __packed; 6702 6703 /** 6704 * struct iwm_add_sta_key_cmd_v1 - add/modify sta key 6705 * @common: see &struct iwm_add_sta_key_common 6706 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6707 * @reserved: reserved 6708 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6709 */ 6710 struct iwm_add_sta_key_cmd_v1 { 6711 struct iwm_add_sta_key_common common; 6712 uint8_t tkip_rx_tsc_byte2; 6713 uint8_t reserved; 6714 uint16_t tkip_rx_ttak[5]; 6715 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */ 6716 6717 /** 6718 * struct iwm_add_sta_key_cmd - add/modify sta key 6719 * @common: see &struct iwm_add_sta_key_common 6720 * @rx_mic_key: TKIP RX unicast or multicast key 6721 * @tx_mic_key: TKIP TX key 6722 * @transmit_seq_cnt: TSC, transmit packet number 6723 */ 6724 struct iwm_add_sta_key_cmd { 6725 struct iwm_add_sta_key_common common; 6726 uint64_t rx_mic_key; 6727 uint64_t tx_mic_key; 6728 uint64_t transmit_seq_cnt; 6729 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */ 6730 6731 /** 6732 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 6733 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 6734 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 6735 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 6736 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 6737 * that doesn't exist. 6738 */ 6739 enum iwm_mvm_add_sta_rsp_status { 6740 IWM_ADD_STA_SUCCESS = 0x1, 6741 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 6742 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 6743 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 6744 }; 6745 6746 /** 6747 * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table 6748 * ( IWM_REMOVE_STA = 0x19 ) 6749 * @sta_id: the station id of the station to be removed 6750 */ 6751 struct iwm_rm_sta_cmd { 6752 uint8_t sta_id; 6753 uint8_t reserved[3]; 6754 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 6755 6756 /** 6757 * struct iwm_mgmt_mcast_key_cmd 6758 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 6759 * @ctrl_flags: %iwm_sta_key_flag 6760 * @IGTK: 6761 * @K1: IGTK master key 6762 * @K2: IGTK sub key 6763 * @sta_id: station ID that support IGTK 6764 * @key_id: 6765 * @receive_seq_cnt: initial RSC/PN needed for replay check 6766 */ 6767 struct iwm_mgmt_mcast_key_cmd { 6768 uint32_t ctrl_flags; 6769 uint8_t IGTK[16]; 6770 uint8_t K1[16]; 6771 uint8_t K2[16]; 6772 uint32_t key_id; 6773 uint32_t sta_id; 6774 uint64_t receive_seq_cnt; 6775 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 6776 6777 struct iwm_wep_key { 6778 uint8_t key_index; 6779 uint8_t key_offset; 6780 uint16_t reserved1; 6781 uint8_t key_size; 6782 uint8_t reserved2[3]; 6783 uint8_t key[16]; 6784 } __packed; 6785 6786 struct iwm_wep_key_cmd { 6787 uint32_t mac_id_n_color; 6788 uint8_t num_keys; 6789 uint8_t decryption_type; 6790 uint8_t flags; 6791 uint8_t reserved; 6792 struct iwm_wep_key wep_key[0]; 6793 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 6794 6795 /* 6796 * BT coex 6797 */ 6798 6799 enum iwm_bt_coex_mode { 6800 IWM_BT_COEX_DISABLE = 0x0, 6801 IWM_BT_COEX_NW = 0x1, 6802 IWM_BT_COEX_BT = 0x2, 6803 IWM_BT_COEX_WIFI = 0x3, 6804 }; /* BT_COEX_MODES_E */ 6805 6806 enum iwm_bt_coex_enabled_modules { 6807 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 6808 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 6809 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 6810 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 6811 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 6812 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 6813 6814 /** 6815 * struct iwm_bt_coex_cmd - bt coex configuration command 6816 * @mode: enum %iwm_bt_coex_mode 6817 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 6818 * 6819 * The structure is used for the BT_COEX command. 6820 */ 6821 struct iwm_bt_coex_cmd { 6822 uint32_t mode; 6823 uint32_t enabled_modules; 6824 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 6825 6826 6827 /* 6828 * Location Aware Regulatory (LAR) API - MCC updates 6829 */ 6830 6831 /** 6832 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 6833 * regulatory profile according to the given MCC (Mobile Country Code). 6834 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6835 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6836 * MCC in the cmd response will be the relevant MCC in the NVM. 6837 * @mcc: given mobile country code 6838 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6839 * @reserved: reserved for alignment 6840 */ 6841 struct iwm_mcc_update_cmd_v1 { 6842 uint16_t mcc; 6843 uint8_t source_id; 6844 uint8_t reserved; 6845 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 6846 6847 /** 6848 * struct iwm_mcc_update_cmd - Request the device to update geographic 6849 * regulatory profile according to the given MCC (Mobile Country Code). 6850 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6851 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6852 * MCC in the cmd response will be the relevant MCC in the NVM. 6853 * @mcc: given mobile country code 6854 * @source_id: the source from where we got the MCC, see iwm_mcc_source 6855 * @reserved: reserved for alignment 6856 * @key: integrity key for MCC API OEM testing 6857 * @reserved2: reserved 6858 */ 6859 struct iwm_mcc_update_cmd { 6860 uint16_t mcc; 6861 uint8_t source_id; 6862 uint8_t reserved; 6863 uint32_t key; 6864 uint32_t reserved2[5]; 6865 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 6866 6867 /** 6868 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 6869 * Contains the new channel control profile map, if changed, and the new MCC 6870 * (mobile country code). 6871 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6872 * @status: see &enum iwm_mcc_update_status 6873 * @mcc: the new applied MCC 6874 * @cap: capabilities for all channels which matches the MCC 6875 * @source_id: the MCC source, see iwm_mcc_source 6876 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6877 * channels, depending on platform) 6878 * @channels: channel control data map, DWORD for each channel. Only the first 6879 * 16bits are used. 6880 */ 6881 struct iwm_mcc_update_resp_v1 { 6882 uint32_t status; 6883 uint16_t mcc; 6884 uint8_t cap; 6885 uint8_t source_id; 6886 uint32_t n_channels; 6887 uint32_t channels[0]; 6888 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 6889 6890 /** 6891 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 6892 * Contains the new channel control profile map, if changed, and the new MCC 6893 * (mobile country code). 6894 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6895 * @status: see &enum iwm_mcc_update_status 6896 * @mcc: the new applied MCC 6897 * @cap: capabilities for all channels which matches the MCC 6898 * @source_id: the MCC source, see iwm_mcc_source 6899 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6900 * @reserved: reserved. 6901 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6902 * channels, depending on platform) 6903 * @channels: channel control data map, DWORD for each channel. Only the first 6904 * 16bits are used. 6905 */ 6906 struct iwm_mcc_update_resp_v2 { 6907 uint32_t status; 6908 uint16_t mcc; 6909 uint8_t cap; 6910 uint8_t source_id; 6911 uint16_t time; 6912 uint16_t reserved; 6913 uint32_t n_channels; 6914 uint32_t channels[0]; 6915 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 6916 6917 #define IWM_GEO_NO_INFO 0 6918 #define IWM_GEO_WMM_ETSI_5GHZ_INFO (1 << 0) 6919 6920 /** 6921 * iwm_mcc_update_resp_v3 - response to MCC_UPDATE_CMD. 6922 * Contains the new channel control profile map, if changed, and the new MCC 6923 * (mobile country code). 6924 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6925 * @status: see &enum iwm_mcc_update_status 6926 * @mcc: the new applied MCC 6927 * @cap: capabilities for all channels which matches the MCC 6928 * @source_id: the MCC source, see IWM_MCC_SOURCE_* 6929 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6930 * @geo_info: geographic specific profile information 6931 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6932 * channels, depending on platform) 6933 * @channels: channel control data map, DWORD for each channel. Only the first 6934 * 16bits are used. 6935 */ 6936 struct iwm_mcc_update_resp_v3 { 6937 uint32_t status; 6938 uint16_t mcc; 6939 uint8_t cap; 6940 uint8_t source_id; 6941 uint16_t time; 6942 uint16_t geo_info; 6943 uint32_t n_channels; 6944 uint32_t channels[0]; 6945 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */ 6946 6947 /** 6948 * struct iwm_mcc_chub_notif - chub notifies of mcc change 6949 * (MCC_CHUB_UPDATE_CMD = 0xc9) 6950 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 6951 * the cellular and connectivity cores that gets updates of the mcc, and 6952 * notifies the ucode directly of any mcc change. 6953 * The ucode requests the driver to request the device to update geographic 6954 * regulatory profile according to the given MCC (Mobile Country Code). 6955 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6956 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6957 * MCC in the cmd response will be the relevant MCC in the NVM. 6958 * @mcc: given mobile country code 6959 * @source_id: identity of the change originator, see iwm_mcc_source 6960 * @reserved1: reserved for alignment 6961 */ 6962 struct iwm_mcc_chub_notif { 6963 uint16_t mcc; 6964 uint8_t source_id; 6965 uint8_t reserved1; 6966 } __packed; /* LAR_MCC_NOTIFY_S */ 6967 6968 enum iwm_mcc_update_status { 6969 IWM_MCC_RESP_NEW_CHAN_PROFILE, 6970 IWM_MCC_RESP_SAME_CHAN_PROFILE, 6971 IWM_MCC_RESP_INVALID, 6972 IWM_MCC_RESP_NVM_DISABLED, 6973 IWM_MCC_RESP_ILLEGAL, 6974 IWM_MCC_RESP_LOW_PRIORITY, 6975 IWM_MCC_RESP_TEST_MODE_ACTIVE, 6976 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 6977 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 6978 }; 6979 6980 enum iwm_mcc_source { 6981 IWM_MCC_SOURCE_OLD_FW = 0, 6982 IWM_MCC_SOURCE_ME = 1, 6983 IWM_MCC_SOURCE_BIOS = 2, 6984 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 6985 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 6986 IWM_MCC_SOURCE_WIFI = 5, 6987 IWM_MCC_SOURCE_RESERVED = 6, 6988 IWM_MCC_SOURCE_DEFAULT = 7, 6989 IWM_MCC_SOURCE_UNINITIALIZED = 8, 6990 IWM_MCC_SOURCE_MCC_API = 9, 6991 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 6992 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 6993 }; 6994 6995 /** 6996 * struct iwm_dts_measurement_notif_v1 - measurements notification 6997 * 6998 * @temp: the measured temperature 6999 * @voltage: the measured voltage 7000 */ 7001 struct iwm_dts_measurement_notif_v1 { 7002 int32_t temp; 7003 int32_t voltage; 7004 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 7005 7006 /** 7007 * struct iwm_dts_measurement_notif_v2 - measurements notification 7008 * 7009 * @temp: the measured temperature 7010 * @voltage: the measured voltage 7011 * @threshold_idx: the trip index that was crossed 7012 */ 7013 struct iwm_dts_measurement_notif_v2 { 7014 int32_t temp; 7015 int32_t voltage; 7016 int32_t threshold_idx; 7017 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 7018 7019 /* 7020 * Some cherry-picked definitions 7021 */ 7022 7023 #define IWM_FRAME_LIMIT 64 7024 7025 /* 7026 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 7027 * As the firmware is slowly running out of command IDs and grouping of 7028 * commands is desirable anyway, the firmware is extending the command 7029 * header from 4 bytes to 8 bytes to introduce a group (in place of the 7030 * former flags field, since that's always 0 on commands and thus can 7031 * be easily used to distinguish between the two). 7032 * 7033 * These functions retrieve specific information from the id field in 7034 * the iwm_host_cmd struct which contains the command id, the group id, 7035 * and the version of the command. 7036 */ 7037 static __inline uint8_t 7038 iwm_cmd_opcode(uint32_t cmdid) 7039 { 7040 return cmdid & 0xff; 7041 } 7042 7043 static __inline uint8_t 7044 iwm_cmd_groupid(uint32_t cmdid) 7045 { 7046 return ((cmdid & 0Xff00) >> 8); 7047 } 7048 7049 static __inline uint8_t 7050 iwm_cmd_version(uint32_t cmdid) 7051 { 7052 return ((cmdid & 0xff0000) >> 16); 7053 } 7054 7055 static __inline uint32_t 7056 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t ver) 7057 { 7058 return opcode + (groupid << 8) + (ver << 16); 7059 } 7060 7061 /* make uint16_t wide id out of uint8_t group and opcode */ 7062 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 7063 7064 /* due to the conversion, this group is special */ 7065 #define IWM_ALWAYS_LONG_GROUP 1 7066 7067 struct iwm_cmd_header { 7068 uint8_t code; 7069 uint8_t flags; 7070 uint8_t idx; 7071 uint8_t qid; 7072 } __packed; 7073 7074 struct iwm_cmd_header_wide { 7075 uint8_t opcode; 7076 uint8_t group_id; 7077 uint8_t idx; 7078 uint8_t qid; 7079 uint16_t length; 7080 uint8_t reserved; 7081 uint8_t version; 7082 } __packed; 7083 7084 /** 7085 * enum iwm_power_scheme 7086 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 7087 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 7088 * @IWM_POWER_LEVEL_LP - Low Power 7089 */ 7090 enum iwm_power_scheme { 7091 IWM_POWER_SCHEME_CAM = 1, 7092 IWM_POWER_SCHEME_BPS, 7093 IWM_POWER_SCHEME_LP 7094 }; 7095 7096 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 7097 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 7098 #define IWM_CMD_FAILED_MSK 0x40 7099 7100 /** 7101 * struct iwm_device_cmd 7102 * 7103 * For allocation of the command and tx queues, this establishes the overall 7104 * size of the largest command we send to uCode, except for commands that 7105 * aren't fully copied and use other TFD space. 7106 */ 7107 struct iwm_device_cmd { 7108 union { 7109 struct { 7110 struct iwm_cmd_header hdr; 7111 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 7112 }; 7113 struct { 7114 struct iwm_cmd_header_wide hdr_wide; 7115 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 7116 sizeof(struct iwm_cmd_header_wide) + 7117 sizeof(struct iwm_cmd_header)]; 7118 }; 7119 }; 7120 } __packed; 7121 7122 struct iwm_rx_packet { 7123 /* 7124 * The first 4 bytes of the RX frame header contain both the RX frame 7125 * size and some flags. 7126 * Bit fields: 7127 * 31: flag flush RB request 7128 * 30: flag ignore TC (terminal counter) request 7129 * 29: flag fast IRQ request 7130 * 28-26: Reserved 7131 * 25: Offload enabled 7132 * 24: RPF enabled 7133 * 23: RSS enabled 7134 * 22: Checksum enabled 7135 * 21-16: RX queue 7136 * 15-14: Reserved 7137 * 13-00: RX frame size 7138 */ 7139 uint32_t len_n_flags; 7140 struct iwm_cmd_header hdr; 7141 uint8_t data[]; 7142 } __packed; 7143 7144 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 7145 #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 7146 #define IWM_FH_RSCSR_FRAME_ALIGN 0x40 7147 #define IWM_FH_RSCSR_RPA_EN (1 << 25) 7148 #define IWM_FH_RSCSR_RADA_EN (1 << 26) 7149 #define IWM_FH_RSCSR_RXQ_POS 16 7150 #define IWM_FH_RSCSR_RXQ_MASK 0x3F0000 7151 7152 static uint32_t 7153 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 7154 { 7155 7156 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 7157 } 7158 7159 static uint32_t 7160 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 7161 { 7162 7163 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 7164 } 7165 7166 #define IWM_MIN_DBM -100 7167 #define IWM_MAX_DBM -33 /* realistic guess */ 7168 7169 /* 7170 * Block paging calculations 7171 */ 7172 #define IWM_PAGE_2_EXP_SIZE 12 /* 4K == 2^12 */ 7173 #define IWM_FW_PAGING_SIZE (1 << IWM_PAGE_2_EXP_SIZE) /* page size is 4KB */ 7174 #define IWM_PAGE_PER_GROUP_2_EXP_SIZE 3 7175 /* 8 pages per group */ 7176 #define IWM_NUM_OF_PAGE_PER_GROUP (1 << IWM_PAGE_PER_GROUP_2_EXP_SIZE) 7177 /* don't change, support only 32KB size */ 7178 #define IWM_PAGING_BLOCK_SIZE (IWM_NUM_OF_PAGE_PER_GROUP * IWM_FW_PAGING_SIZE) 7179 /* 32K == 2^15 */ 7180 #define IWM_BLOCK_2_EXP_SIZE (IWM_PAGE_2_EXP_SIZE + IWM_PAGE_PER_GROUP_2_EXP_SIZE) 7181 7182 /* 7183 * Image paging calculations 7184 */ 7185 #define IWM_BLOCK_PER_IMAGE_2_EXP_SIZE 5 7186 /* 2^5 == 32 blocks per image */ 7187 #define IWM_NUM_OF_BLOCK_PER_IMAGE (1 << IWM_BLOCK_PER_IMAGE_2_EXP_SIZE) 7188 /* maximum image size 1024KB */ 7189 #define IWM_MAX_PAGING_IMAGE_SIZE (IWM_NUM_OF_BLOCK_PER_IMAGE * IWM_PAGING_BLOCK_SIZE) 7190 7191 /* Virtual address signature */ 7192 #define IWM_PAGING_ADDR_SIG 0xAA000000 7193 7194 #define IWM_PAGING_CMD_IS_SECURED (1 << 9) 7195 #define IWM_PAGING_CMD_IS_ENABLED (1 << 8) 7196 #define IWM_PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS 0 7197 #define IWM_PAGING_TLV_SECURE_MASK 1 7198 7199 #define IWM_READ(sc, reg) \ 7200 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 7201 7202 #define IWM_WRITE(sc, reg, val) \ 7203 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 7204 7205 #define IWM_WRITE_1(sc, reg, val) \ 7206 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 7207 7208 #define IWM_SETBITS(sc, reg, mask) \ 7209 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 7210 7211 #define IWM_CLRBITS(sc, reg, mask) \ 7212 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 7213 7214 #define IWM_BARRIER_WRITE(sc) \ 7215 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 7216 BUS_SPACE_BARRIER_WRITE) 7217 7218 #define IWM_BARRIER_READ_WRITE(sc) \ 7219 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 7220 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 7221
Indexes created Sat Feb 21 16:20:20 UTC 2026