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Searched
refs:Idx1
(Results
1 - 12
of
12
) sorted by relevancy
/src/external/apache2/llvm/dist/llvm/lib/Analysis/
StratifiedSets.h
441
void merge(StratifiedIndex
Idx1
, StratifiedIndex Idx2) {
442
assert(inbounds(
Idx1
) && inbounds(Idx2));
443
assert(&linksAt(
Idx1
) != &linksAt(Idx2) &&
446
// CASE 1: If the set at `
Idx1
` is above or below `Idx2`, we need to merge
449
if (tryMergeUpwards(
Idx1
, Idx2))
452
if (tryMergeUpwards(Idx2,
Idx1
))
455
// CASE 2: The set at `
Idx1
` is not in the same chain as the set at `Idx2`.
457
mergeDirect(
Idx1
, Idx2);
460
/// Merges two sets assuming that the set at `
Idx1
` is unreachable from
462
void mergeDirect(StratifiedIndex
Idx1
, StratifiedIndex Idx2)
[
all
...]
/src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp
168
bool NewMI, unsigned
Idx1
,
176
unsigned CommutableOpIdx1 =
Idx1
; (void)CommutableOpIdx1;
179
CommutableOpIdx1 ==
Idx1
&& CommutableOpIdx2 == Idx2 &&
181
assert(MI.getOperand(
Idx1
).isReg() && MI.getOperand(Idx2).isReg() &&
185
Register Reg1 = MI.getOperand(
Idx1
).getReg();
188
unsigned SubReg1 = MI.getOperand(
Idx1
).getSubReg();
190
bool Reg1IsKill = MI.getOperand(
Idx1
).isKill();
192
bool Reg1IsUndef = MI.getOperand(
Idx1
).isUndef();
194
bool Reg1IsInternal = MI.getOperand(
Idx1
).isInternalRead();
199
? MI.getOperand(
Idx1
).isRenamable(
[
all
...]
ShadowStackGCLowering.cpp
82
Type *Ty, Value *BasePtr, int
Idx1
,
85
Type *Ty, Value *BasePtr, int
Idx1
, int Idx2,
PeepholeOptimizer.cpp
272
RecurrenceInstr(MachineInstr *MI, unsigned
Idx1
, unsigned Idx2)
273
: MI(MI), CommutePair(std::make_pair(
Idx1
, Idx2)) {}
/src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGBuilder.h
269
Address CreateConstInBoundsGEP2_32(Address Addr, unsigned Idx0, unsigned
Idx1
,
274
Addr.getElementType(), Addr.getPointer(), Idx0,
Idx1
, Name));
CGBuiltin.cpp
9889
llvm::Value *
Idx1
= llvm::ConstantInt::get(SizeTy, 1);
9891
Value *Op1 = Builder.CreateExtractElement(Vec,
Idx1
, "lane1");
9901
llvm::Value *
Idx1
= llvm::ConstantInt::get(SizeTy, 1);
9903
Value *Op1 = Builder.CreateExtractElement(Vec,
Idx1
, "lane1");
9913
llvm::Value *
Idx1
= llvm::ConstantInt::get(SizeTy, 1);
9915
Value *Op1 = Builder.CreateExtractElement(Vec,
Idx1
, "lane1");
/src/external/apache2/llvm/dist/llvm/include/llvm/IR/
IRBuilder.h
1851
Value *CreateConstGEP2_32(Type *Ty, Value *Ptr, unsigned Idx0, unsigned
Idx1
,
1855
ConstantInt::get(Type::getInt32Ty(Context),
Idx1
)
1865
unsigned
Idx1
, const Twine &Name = "") {
1868
ConstantInt::get(Type::getInt32Ty(Context),
Idx1
)
1906
Value *CreateConstGEP2_64(Type *Ty, Value *Ptr, uint64_t Idx0, uint64_t
Idx1
,
1910
ConstantInt::get(Type::getInt64Ty(Context),
Idx1
)
1919
Value *CreateConstGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t
Idx1
,
1921
return CreateConstGEP2_64(nullptr, Ptr, Idx0,
Idx1
, Name);
1925
uint64_t
Idx1
, const Twine &Name = "") {
1928
ConstantInt::get(Type::getInt64Ty(Context),
Idx1
)
[
all
...]
/src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonVectorCombine.cpp
1332
Value *
Idx1
= Gep1->getOperand(1);
1336
Simplify(CallBuilder(B, CreateSub(Idx0,
Idx1
)))))
1340
KnownBits Known1 = computeKnownBits(
Idx1
, DL, 0, &AC, Gep1, &DT);
1347
Value *AndU1 = Simplify(CallBuilder(B, CreateAnd(
Idx1
, MaskU)));
1358
Value *AndK1 = Simplify(CallBuilder(B, CreateAnd(
Idx1
, MaskK)));
/src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.cpp
1395
CodeGenSubRegIndex *
Idx1
= I1.first;
1401
// Try composing
Idx1
with another SubRegIndex.
1413
if (CodeGenSubRegIndex *Prev =
Idx1
->addComposite(Idx2, Idx3)) {
1415
if (!UserDefined.count({
Idx1
, Idx2}) ||
1416
agree(compose(
Idx1
, Idx2), SubRegAction.at(Idx3)))
1417
PrintWarning(Twine("SubRegIndex ") +
Idx1
->getQualifiedName() +
/src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp
986
// DS_WRITE_B32 addr, f(w),
idx1
1560
unsigned
Idx1
;
1566
Idx1
= Idxs[0][Paired.Width - 1];
1570
Idx1
= Idxs[CI.Width][Paired.Width - 1];
1573
return std::make_pair(Idx0,
Idx1
);
SIISelLowering.cpp
5546
const int
Idx1
= SVN->getMaskElt(I + 1);
5548
int VecIdx1 =
Idx1
< SrcNumElts ? 0 : 1;
5550
int EltIdx1 =
Idx1
< SrcNumElts ?
Idx1
:
Idx1
- SrcNumElts;
10617
SDValue
Idx1
= Op1.getOperand(1);
10638
if (
Idx1
!= Op2.getOperand(1) || Idx2 != FMAOp2.getOperand(1) ||
10639
//
Idx1
and Idx2 cannot be the same.
10640
Idx1
== Idx2)
/src/external/apache2/llvm/dist/clang/lib/AST/
Expr.cpp
3984
auto
Idx1
= Array1->getIdx();
3986
const auto Integer1 = dyn_cast<IntegerLiteral>(
Idx1
);
3993
if (!isSameComparisonOperand(
Idx1
, Idx2))
Completed in 93 milliseconds
Indexes created Sat Sep 26 00:25:34 UTC 2026