| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) {
74 switch ((Imm >> 6) & 0x7) {
85 static inline unsigned getShiftValue(unsigned Imm) {
86 return Imm & 0x3f;
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) {
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
110 return (STEnc << 6) | (Imm & 0x3f)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVMatInt.h | 21 int64_t Imm;
23 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 32 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize,
34 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
38 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize,
40 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
44 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize,
46 unsigned Shamt = countTrailingZeros(Imm);
47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
51 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize
[all...] |
| MipsAnalyzeImmediate.h | 26 /// Analyze - Get an instruction sequence to load immediate Imm. The last
29 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
38 /// load immediate Imm
39 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
42 /// load immediate Imm
43 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
46 /// load immediate Imm
47 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
49 /// GetInstSeqLs - Get instruction sequences to load immediate Imm.
50 void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs)
[all...] |
| MipsISelDAGToDAG.h | 57 /// (reg + imm).
98 virtual bool selectVSplat(SDNode *N, APInt &Imm,
101 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
103 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
105 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
107 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
109 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
111 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
113 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
115 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const
[all...] |
| MipsSEISelDAGToDAG.h | 96 bool selectVSplat(SDNode *N, APInt &Imm,
99 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
102 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
104 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
106 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
108 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
110 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
112 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
114 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
116 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override
[all...] |
| MipsISelDAGToDAG.cpp | 154 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
160 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
165 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
170 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
175 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
180 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
185 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
190 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
195 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
200 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm
109 // reg, the second is the shift amount (or reg0 if not present or imm). The
110 // third operand encodes the shift opcode and the imm if a reg isn't present.
112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
118 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
119 /// the 8-bit imm value.
120 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86ShuffleDecode.h | 31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm,
55 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm,
58 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm,
61 void DecodeVALIGNMask(unsigned NumElts, unsigned Imm,
65 void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
69 void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm,
73 void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm,
80 void DecodeSHUFPMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
104 void DecodeBLENDMask(unsigned NumElts, unsigned Imm,
[all...] |
| X86ShuffleDecode.cpp | 25 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
33 unsigned ZMask = Imm & 15;
34 unsigned CountD = (Imm >> 4) & 3;
35 unsigned CountS = (Imm >> 6) & 3;
98 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm,
105 if (i >= Imm) M = i - Imm + l;
110 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm,
116 unsigned Base = i + Imm;
123 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandImm.h | 28 void expandMOVImm(uint64_t Imm, unsigned BitSize,
|
| AArch64ExpandImm.cpp | 22 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) {
25 return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
125 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
130 Imm &= ~(Mask << (Idx * 16));
133 Imm |= Mask << (Idx * 16);
135 return Imm;
245 static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
259 Imm = ~Imm;
264 Imm &= (1LL << 32) - 1
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
75 int32_t Offset = SignExtend32<24>(Imm);
194 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
196 assert(isUInt<N>(Imm) && "Invalid immediate");
197 Inst.addOperand(MCOperand::createImm(Imm));
202 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
204 assert(isUInt<N>(Imm) && "Invalid immediate");
205 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiTargetTransformInfo.h | 52 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
55 if (Imm == 0)
57 if (isInt<16>(Imm.getSExtValue()))
59 if (isInt<21>(Imm.getZExtValue()))
61 if (isInt<32>(Imm.getSExtValue())) {
62 if ((Imm.getSExtValue() & 0xFFFF) == 0)
71 const APInt &Imm, Type *Ty,
74 return getIntImmCost(Imm, Ty, CostKind);
78 const APInt &Imm, Type *Ty,
80 return getIntImmCost(Imm, Ty, CostKind)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| NVPTXInstPrinter.cpp | 91 O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
101 int64_t Imm = MO.getImm();
105 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
109 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
113 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
151 int64_t Imm = MO.getImm();
155 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
158 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
225 int Imm = (int) MO.getImm();
227 if (Imm)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| AMDGPUInstPrinter.cpp | 73 int64_t Imm = MI->getOperand(OpNo).getImm();
74 if (isInt<16>(Imm) || isUInt<16>(Imm))
75 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
134 uint16_t Imm = MI->getOperand(OpNo).getImm();
135 if (Imm != 0) {
144 uint16_t Imm = MI->getOperand(OpNo).getImm();
145 if (Imm != 0) {
207 auto Imm = MI->getOperand(OpNo).getImm();
208 if (Imm & CPol::GLC
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 171 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
172 if (!isUInt<N>(Imm))
174 Inst.addOperand(MCOperand::createImm(Imm));
179 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
180 if (!isUInt<N>(Imm))
182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
186 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
188 return decodeUImmOperand<1>(Inst, Imm);
191 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm,
193 return decodeUImmOperand<2>(Inst, Imm);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFInstPrinter.cpp | 76 auto Imm = OffsetOp.getImm();
77 if (Imm >= 0)
78 O << " + " << formatImm(Imm);
80 O << " - " << formatImm(-Imm);
101 int16_t Imm = Op.getImm();
102 O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVTargetTransformInfo.cpp | 18 InstructionCost RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
24 if (Imm == 0)
29 return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty),
34 const APInt &Imm, Type *Ty,
41 if (Imm == 0)
77 if (Imm.getMinSignedBits() <= 64 &&
78 getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
84 return getIntImmCost(Imm, Ty, CostKind);
93 const APInt &Imm, Type *Ty,
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MIRFormatter.h | 42 Optional<unsigned> OpIdx, int64_t Imm) const {
43 OS << Imm;
49 StringRef Src, int64_t &Imm,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFTargetTransformInfo.h | 40 int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) {
41 if (Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegNumbering.cpp | 78 int64_t Imm = MI.getOperand(1).getImm();
80 << " -> WAReg " << Imm << "\n");
81 MFI.setWAReg(MI.getOperand(0).getReg(), Imm);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiMCTargetDesc.cpp | 103 int64_t Imm = Inst.getOperand(0).getImm();
104 Target = Addr + Size + Imm;
107 int64_t Imm = Inst.getOperand(0).getImm();
111 if (Imm == 0)
114 Target = Imm;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/ |
| RISCVAsmParser.cpp | 293 ImmOp Imm;
311 Imm = o.Imm;
340 static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
344 return RE->evaluateAsConstant(Imm);
349 Imm = CE->getValue();
359 int64_t Imm;
363 bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
368 IsValid = isShiftedInt<N - 1, 1>(Imm);
375 int64_t Imm;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/ |
| AMDGPUDisassembler.cpp | 71 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
77 APInt SignedOffset(18, Imm * 4, true);
82 return addOperand(Inst, MCOperand::createImm(Imm));
85 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm,
90 Offset = Imm & 0xFFFFF;
92 Offset = SignExtend64<21>(Imm);
105 unsigned Imm, \
109 return addOperand(Inst, DAsm->DecoderName(Imm)); \
148 unsigned Imm,
152 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
[all...] |
