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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMAddressingModes.h 437 // addrmode3 := reg +/- imm8
483 // addrmode5 := reg +/- imm8*4
504 // addrmode5fp16 := reg +/- imm8*2
559 unsigned Imm8 = getVMOVModImmVal(ModImm);
564 Val = Imm8;
569 Val = Imm8 << (8 * ByteNum);
574 Val = Imm8 << (8 * ByteNum);
579 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
ARMMCCodeEmitter.cpp 186 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
198 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
295 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
300 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1109 /// 'reg +/- imm8<<2' operand.
1116 // {7-0} = imm8
1117 unsigned Reg, Imm8;
1123 Imm8 = 0;
1133 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1141 uint32_t Binary = (Imm8 >> 2) & 0xff
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/
M68kBaseInfo.h 63 Imm8 = 0xA,
M68kMCCodeEmitter.cpp 216 case M68kBeads::Imm8:
361 case M68kBeads::Imm8:
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/
M68kDisassembler.cpp 345 case M68kBeads::Imm8:
440 case M68kBeads::Imm8:
538 case M68kBeads::Imm8:
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h 817 /// storing a classifier in the imm8 field. To simplify our implementation,
836 Imm8 = 1 << ImmShift,
989 case X86II::Imm8:
1010 case X86II::Imm8:
1027 case X86II::Imm8:
  /src/external/gpl3/gdb.old/dist/opcodes/
i386-opc.h 865 Imm8,
936 unsigned int imm8:1;
i386-gen.c 542 BITFIELD (Imm8),
  /src/external/gpl3/binutils/dist/opcodes/
i386-opc.h 912 Imm8,
983 unsigned int imm8:1;
i386-gen.c 592 BITFIELD (Imm8),
  /src/external/gpl3/binutils.old/dist/opcodes/
i386-opc.h 899 Imm8,
970 unsigned int imm8:1;
i386-gen.c 572 BITFIELD (Imm8),
  /src/external/gpl3/gdb/dist/opcodes/
i386-opc.h 899 Imm8,
970 unsigned int imm8:1;
i386-gen.c 572 BITFIELD (Imm8),
  /src/external/gpl3/gdb/dist/sim/testsuite/h8300/
movw.s 175 mov_w_imm8_to_postinc: ; post-increment from imm8 to mem
181 mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands.
207 mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem
213 mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands.
245 mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands
277 mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands
309 mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand
movb.s 150 mov_b_imm8_to_postinc: ; post-increment from imm8 to mem
156 mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands.
182 mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem
188 mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands.
220 mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands
252 mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands
284 mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
movl.s 138 mov_l_imm8_to_postinc: ; post-increment from imm8 to mem
144 mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands.
170 mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem
176 mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands.
208 mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands
240 mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands
272 mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand
  /src/external/gpl3/gdb.old/dist/sim/testsuite/h8300/
movw.s 175 mov_w_imm8_to_postinc: ; post-increment from imm8 to mem
181 mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands.
207 mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem
213 mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands.
245 mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands
277 mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands
309 mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand
movb.s 150 mov_b_imm8_to_postinc: ; post-increment from imm8 to mem
156 mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands.
182 mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem
188 mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands.
220 mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands
252 mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands
284 mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
movl.s 138 mov_l_imm8_to_postinc: ; post-increment from imm8 to mem
144 mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands.
170 mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem
176 mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands.
208 mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands
240 mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands
272 mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 3272 assert(CE && "non-constant post-idx-imm8 operand!");
6835 // Thumb1 imm8 sub / add
8112 unsigned Imm8 = Inst.getOperand(0).getImm();
8116 if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
8120 if (Imm8 == 0x14 && Pred != ARMCC::AL)

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