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    Searched refs:ImmOffset (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 70 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
118 /// EVEX instructions. \p will be set to the value to pass to the ImmOffset
120 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {
136 // ImmOffset will be added to Value in emitImmediate leaving just CDisp8.
137 ImmOffset = CDisp8 - Value;
292 int ImmOffset) const {
299 emitConstant(DispOp.getImm() + ImmOffset, Size, OS);
307 // If we have an immoffset, add it to the expression.
312 assert(ImmOffset == 0);
322 ImmOffset = static_cast<int>(OS.tell() - StartByte)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 1339 uint32_t SOffset, ImmOffset;
1340 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget,
1344 InstOffsetVal = ImmOffset;
1348 return SOffset + ImmOffset;
1358 uint32_t SOffset, ImmOffset;
1359 if ((int)Offset > 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset,
1365 InstOffsetVal = ImmOffset;
1374 InstOffsetVal = ImmOffset;
1451 int64_t ImmOffset = 0;
1454 VOffset, SOffset, ImmOffset, Alignment)
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AMDGPUISelDAGToDAG.cpp 196 SDValue &SOffset, SDValue &ImmOffset) const;
1522 SDValue &ImmOffset) const {
1548 ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16);
1579 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1586 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1784 int64_t ImmOffset = 0;
1797 ImmOffset = COffsetVal;
1854 Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i16);
1870 Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i16);
2491 int ImmOffset = 0
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AMDGPUInstructionSelector.cpp 1334 unsigned ImmOffset;
1356 ImmOffset = OffsetDef->getOperand(1).getCImm()->getZExtValue();
1360 std::tie(BaseOffset, ImmOffset) =
1398 MIB.addImm(ImmOffset)
3521 int64_t ImmOffset = 0;
3531 ImmOffset = ConstOffset;
3605 MIB.addImm(ImmOffset);
3629 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset
3638 int64_t ImmOffset = 0;
3648 ImmOffset = ConstOffset
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AMDGPUInstructionSelector.h 251 Register &SOffset, int64_t &ImmOffset) const;
AMDGPULegalizerInfo.cpp 3527 // split between the instruction's voffset and immoffset fields) and soffset
3530 // offset and figures out how to split it between voffset and immoffset.
3543 unsigned ImmOffset = TotalConstOffset;
3549 // If the immediate value is too big for the immoffset field, put the value
3550 // and -4096 into the immoffset field so that the value that is copied/added
3556 unsigned Overflow = ImmOffset & ~MaxImm;
3557 ImmOffset -= Overflow;
3559 Overflow += ImmOffset;
3560 ImmOffset = 0;
3575 return std::make_tuple(BaseReg, ImmOffset, TotalConstOffset)
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SIISelLowering.cpp 7808 // split between the instruction's voffset and immoffset fields) and soffset
7811 // offset and figures out how to split it between voffset and immoffset.
7827 unsigned ImmOffset = C1->getZExtValue();
7828 // If the immediate value is too big for the immoffset field, put the value
7829 // and -4096 into the immoffset field so that the value that is copied/added
7835 unsigned Overflow = ImmOffset & ~MaxImm;
7836 ImmOffset -= Overflow;
7838 Overflow += ImmOffset;
7839 ImmOffset = 0;
7841 C1 = cast<ConstantSDNode>(DAG.getTargetConstant(ImmOffset, DL, MVT::i32))
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  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFrameLowering.cpp 857 const int ImmOffset = MFI.getObjectOffset(SaveIndex);
858 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
860 assert(((ImmOffset & 0x7) == 0) &&
864 .addImm(ImmOffset)
1859 const int ImmOffset = MFI.getObjectOffset(SaveIndex);
1860 assert((ImmOffset <= -8 && ImmOffset >= -512) &&
1862 assert(((ImmOffset & 0x7) == 0) &&
1866 .addImm(ImmOffset)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ExpandPseudoInsts.cpp 644 int ImmOffset = MI.getOperand(2).getImm() + Offset;
646 assert(ImmOffset >= -256 && ImmOffset < 256 &&
653 .addImm(ImmOffset);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUBaseInfo.h 889 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
AMDGPUBaseInfo.cpp 1883 // Given Imm, split it into the values to put into the SOffset and ImmOffset
1889 // offsets within the given alignment can be added to the resulting ImmOffset.
1890 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1924 ImmOffset = Imm;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 3828 SDValue Base, RegOffset, ImmOffset;
3831 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset);
3840 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain};
3857 SDValue Base, RegOffset, ImmOffset;
3860 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset);
3871 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain};

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