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    Searched refs:ImmOp (Results 1 - 25 of 36) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonOptAddrMode.cpp 107 bool changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
109 bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum);
111 const MachineOperand &ImmOp, unsigned ImmOpNum);
413 const MachineOperand ImmOp = AddMI->getOperand(2);
425 OffsetOp.setImm(ImmOp.getImm() + OffsetOp.getImm());
483 bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
502 MIB.add(ImmOp);
511 const GlobalValue *GV = ImmOp.getGlobal();
512 int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(2).getImm();
514 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags())
    [all...]
HexagonAsmPrinter.cpp 255 MCOperand &ImmOp = Inst.getOperand(i);
256 const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr());
HexagonConstExtenders.cpp 1778 const MachineOperand &ImmOp = MI.getOperand(IsAddi ? 2 : 1);
1779 assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&
1895 MachineOperand &ImmOp = P.first->getOperand(J+1);
1896 ImmOp.setImm(ImmOp.getImm() + Diff);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineDebugify.cpp 131 auto ImmOp = MachineOperand::CreateImm(NextImm++);
133 /*IsIndirect=*/false, ImmOp, LocalVar, Expr);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVMergeBaseOffset.cpp 246 MachineOperand &ImmOp = LoADDI.getOperand(2);
247 ImmOp.setOffset(Offset);
248 Tail.addOperand(ImmOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFMISimplifyPatchable.cpp 123 const MachineOperand &ImmOp = DefInst->getOperand(2);
124 if (!ImmOp.isImm() || ImmOp.getImm() != 0)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallFrameOptimization.cpp 291 const MachineOperand &ImmOp = MI->getOperand(X86::AddrNumOperands);
292 return ImmOp.getImm() == 0 ? Convert : Exit;
297 const MachineOperand &ImmOp = MI->getOperand(X86::AddrNumOperands);
298 return ImmOp.getImm() == -1 ? Convert : Exit;
X86MCInstLower.cpp 320 unsigned ImmOp = Inst.getNumOperands() - 1;
322 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
334 MCOperand Saved = Inst.getOperand(ImmOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ThumbRegisterInfo.cpp 393 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
400 ImmOp.ChangeToImmediate(ImmedOffset);
417 ImmOp.ChangeToImmediate(0);
421 ImmOp.ChangeToImmediate(ImmedOffset);
ARMBaseInstrInfo.h 857 unsigned ImmOp;
860 ImmOp = 2;
864 ImmOp = 2;
869 ImmOp = 3;
875 return Scale * MI.getOperand(ImmOp).getImm();
Thumb2InstrInfo.cpp 699 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
726 ImmOp.ChangeToImmediate(ImmedOffset);
744 ImmOp.ChangeToImmediate(ImmedOffset);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelDAGToDAG.cpp 241 SDValue ImmOp = Op->getOperand(1);
242 ConstantSDNode *ImmNode = dyn_cast<ConstantSDNode>(ImmOp);
281 Disp = ImmOp;
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/
BPFAsmParser.cpp 93 struct ImmOp {
101 ImmOp Imm;
  /src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/AsmParser/
CSKYAsmParser.cpp 94 struct ImmOp {
102 ImmOp Imm;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp 310 const MachineOperand *ImmOp =
312 if (!ImmOp->isImm())
329 Imm = ImmOp->getImm();
SIFoldOperands.cpp 930 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
931 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII);
1432 const MachineOperand *ImmOp = nullptr;
1436 ImmOp = Src0;
1439 ImmOp = Src1;
1444 int OMod = getOModValue(Op, ImmOp->getImm());
AMDGPUInstructionSelector.cpp 2100 MachineOperand &ImmOp = I.getOperand(1);
2105 if (ImmOp.isFPImm()) {
2106 const APInt &Imm = ImmOp.getFPImm()->getValueAPF().bitcastToAPInt();
2107 ImmOp.ChangeToImmediate(Imm.getZExtValue());
2108 } else if (ImmOp.isCImm()) {
2109 ImmOp.ChangeToImmediate(ImmOp.getCImm()->getSExtValue());
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 618 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
619 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
620 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
715 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
719 int64_t ImmOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
X86Operand.h 52 struct ImmOp {
75 struct ImmOp Imm;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/
LanaiAsmParser.cpp 126 struct ImmOp {
140 struct ImmOp Imm;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
MachineIRBuilder.cpp 491 int64_t ImmOp) {
494 ResTy, APInt::getLowBitsSet(ResTy.getScalarSizeInBits(), ImmOp));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/
SparcAsmParser.cpp 242 struct ImmOp {
255 struct ImmOp Imm;
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/
VEAsmParser.cpp 176 struct ImmOp {
203 struct ImmOp Imm;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 864 struct ImmOp {
880 struct ImmOp Imm;
2864 const MCOperand &ImmOp = Inst.getOperand(1);
2865 assert(ImmOp.isImm() && "expected immediate operand kind");
2869 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
3617 const MCOperand &ImmOp = Inst.getOperand(1);
3618 assert(ImmOp.isImm() && "expected immediate operand kind");
3647 int64_t ImmValue = ImmOp.getImm();
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/
PPCAsmParser.cpp 184 struct ImmOp {
199 struct ImmOp Imm;

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