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    Searched refs:ImmReg (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 2213 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2215 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2216 return ImmReg;
2233 unsigned ImmReg = createResultReg(RC);
2234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2236 return ImmReg;
2395 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2397 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2398 return ImmReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 1087 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1088 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
1095 .addReg(ImmReg)
1181 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1182 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
1189 .addReg(ImmReg)
R600ISelLowering.cpp 2064 unsigned ImmReg = R600::ALU_LITERAL_X;
2071 ImmReg = R600::ZERO;
2073 ImmReg = R600::HALF;
2075 ImmReg = R600::ONE;
2083 ImmReg = R600::ZERO;
2085 ImmReg = R600::ONE_INT;
2094 if (ImmReg == R600::ALU_LITERAL_X) {
2102 Src = DAG.getRegister(ImmReg, MVT::i32);
SIInstrInfo.cpp 6704 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6709 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6713 .addReg(ImmReg, RegState::Kill)
6723 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6724 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6727 .addReg(ImmReg, RegState::Kill)
6733 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6738 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6742 .addReg(ImmReg, RegState::Kill)
AMDGPUInstructionSelector.cpp 1896 Register ImmReg = MRI->createVirtualRegister(DstRC);
1911 BuildMI(*MBB, I, DL, TII.get(MovOpc), ImmReg)
1915 .addReg(ImmReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFastISel.cpp 465 unsigned ImmReg = createResultReg(RC);
467 TII.get(Opc), ImmReg)
469 return ImmReg;
481 unsigned ImmReg = createResultReg(RC);
483 TII.get(Opc), ImmReg)
485 return ImmReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 4601 unsigned ImmReg = DstReg;
4606 ImmReg = ATReg;
4609 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4613 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI);
4631 unsigned ImmReg = DstReg;
4654 ImmReg = ATReg;
4657 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4661 // $SrcReg > $ImmReg is equal to $ImmReg < $SrcReg
4662 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitSimplify.cpp 1489 Register ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL);
1490 if (ImmReg) {
1491 HBS::replaceReg(DR, ImmReg, MRI);
1492 BT.put(ImmReg, DRC);

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